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Tue, 30 May 2023 17:30:47 +0000 (GMT) Message-ID: <38fdc4d6-ab1d-c305-c42f-0efab30c23a5@linux.ibm.com> Date: Tue, 30 May 2023 19:30:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20230530161129.313258-1-fbarrat@linux.ibm.com> <20230530161129.313258-5-fbarrat@linux.ibm.com> From: Frederic Barrat In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Qg3hjRzLOObAlCAkRL3qhqA43YpIzjdU X-Proofpoint-ORIG-GUID: 3vDikFwXOlB0DzX5V3FZP5snx0Kuvnbp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_12,2023-05-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 mlxlogscore=780 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305300135 Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/05/2023 18:49, Cédric Le Goater wrote: > On 5/30/23 18:40, Cédric Le Goater wrote: >> On 5/30/23 18:11, Frederic Barrat wrote: >>> The Thread Interrupt Management Area (TIMA) can be accessed through 4 >>> ports/snoop buses, targeted by the address. The base address of a TIMA >>> is using port 0 and the other ports are 0x80 apart. Using one port or >>> another can be useful to balance the load on the snoop buses. >> >> and can we have some nice examples of how these ports are used ? only for >> snooping or also for balancing operations ? which ones ? >> >>> The TIMA registers are in the 0x0 -> 0x3F range and there are 2 >>> indication bits for special operations (bits 10 and 11; everything >>> fits on a 4k page). So the port address bits fall in between and are >>> "don't care" for the hardware when processing the TIMA operation. So >>> this patch filters out those port address bits so that a TIMA >>> operation can be triggered using any port. >>> >>> It is also true for indirect access (through the IC BAR) and it's >>> actually nothing new, it was already the case on P9. Which helps here, >>> as the TIMA handling code is common between P9 (xive) and P10 (xive2). >>> >>> Signed-off-by: Frederic Barrat >> >> Reviewed-by: Cédric Le Goater > > one extra comment, since we already have one mask for the tima offsets : > >     /* >      * First, check for special operations in the 2K region >      */ >     if (offset & 0x800) { > > I think it would be cleaner to add some defines in the reg definition file. Yeah, you're right, I should respin it with some proper defines. And I'll add one for the special op bit(s). Fred > > Can come later. > > Thanks, > > C. >