From: Max Chou <max.chou@sifive.com>
To: Anton Blanchard <antonb@tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Date: Fri, 7 Feb 2025 17:45:23 +0800 [thread overview]
Message-ID: <391b0fdb-b5f7-4151-ad84-0718a197dcee@sifive.com> (raw)
In-Reply-To: <20250126072056.4004912-12-antonb@tenstorrent.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
On 2025/1/26 3:20 PM, Anton Blanchard wrote:
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 312d8b1b81..2741f8bd8e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2410,10 +2410,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
> }
>
> /* OPFVF with WIDEN */
> -#define GEN_OPFVF_WIDEN_TRANS(NAME) \
> +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
> static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> { \
> - if (opfvf_widen_check(s, a)) { \
> + if (CHECK(s, a)) { \
> uint32_t data = 0; \
> static gen_helper_opfvf *const fns[2] = { \
> gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
> @@ -2429,8 +2429,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> return false; \
> }
>
> -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
>
> static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
> {
> @@ -2512,7 +2512,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
>
> /* Vector Widening Floating-Point Multiply */
> GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
>
> /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
> GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
> @@ -2537,10 +2537,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
> GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
>
> /* Vector Floating-Point Square-Root Instruction */
>
next prev parent reply other threads:[~2025-02-07 9:45 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-26 7:20 [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases Anton Blanchard
2025-01-26 7:20 ` [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register Anton Blanchard
2025-02-07 9:26 ` Max Chou
2025-01-26 7:20 ` [PATCH 02/12] target/riscv: handle vrgather mask and source overlap Anton Blanchard
2025-02-07 9:33 ` Max Chou
2025-01-26 7:20 ` [PATCH 03/12] target/riscv: handle vadd.vx form " Anton Blanchard
2025-02-07 9:37 ` Max Chou
2025-01-26 7:20 ` [PATCH 04/12] target/riscv: handle vadd.vv " Anton Blanchard
2025-01-26 7:20 ` [PATCH 05/12] target/riscv: handle vslide1down.vx " Anton Blanchard
2025-02-07 9:39 ` Max Chou
2025-01-26 7:20 ` [PATCH 06/12] target/riscv: handle vzext.vf2 " Anton Blanchard
2025-01-26 7:20 ` [PATCH 07/12] target/riscv: handle vwadd.vx " Anton Blanchard
2025-01-26 7:20 ` [PATCH 08/12] target/riscv: handle vwadd.vv " Anton Blanchard
2025-01-26 7:20 ` [PATCH 09/12] target/riscv: handle vwadd.wv " Anton Blanchard
2025-01-26 7:20 ` [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap Anton Blanchard
2025-02-07 9:42 ` Max Chou
2025-01-26 7:20 ` [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS Anton Blanchard
2025-02-07 9:45 ` Max Chou [this message]
2025-01-26 7:20 ` [PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite Anton Blanchard
2025-02-27 14:47 ` [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases Max Chou
2025-03-17 2:08 ` [CAUTION - External Sender] " Anton Blanchard
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