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[218.166.198.8]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048e1e80fsm2584260b3a.157.2025.02.07.01.45.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2025 01:45:26 -0800 (PST) Message-ID: <391b0fdb-b5f7-4151-ad84-0718a197dcee@sifive.com> Date: Fri, 7 Feb 2025 17:45:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS To: Anton Blanchard , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei References: <20250126072056.4004912-1-antonb@tenstorrent.com> <20250126072056.4004912-12-antonb@tenstorrent.com> Content-Language: en-US From: Max Chou In-Reply-To: <20250126072056.4004912-12-antonb@tenstorrent.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Max Chou On 2025/1/26 3:20 PM, Anton Blanchard wrote: > Signed-off-by: Anton Blanchard > --- > target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 312d8b1b81..2741f8bd8e 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2410,10 +2410,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) > } > > /* OPFVF with WIDEN */ > -#define GEN_OPFVF_WIDEN_TRANS(NAME) \ > +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \ > static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > { \ > - if (opfvf_widen_check(s, a)) { \ > + if (CHECK(s, a)) { \ > uint32_t data = 0; \ > static gen_helper_opfvf *const fns[2] = { \ > gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ > @@ -2429,8 +2429,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > return false; \ > } > > -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check) > > static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) > { > @@ -2512,7 +2512,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) > > /* Vector Widening Floating-Point Multiply */ > GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) > -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check) > > /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ > GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) > @@ -2537,10 +2537,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) > GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) > -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) > -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) > +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check) > +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check) > > /* Vector Floating-Point Square-Root Instruction */ >