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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id e17-20020adfe7d1000000b00300aee6c9cesm61518wrn.20.2023.05.16.10.19.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 10:19:05 -0700 (PDT) Message-ID: <392f50f5-9d59-bd01-c7a1-115c351b5d60@redhat.com> Date: Tue, 16 May 2023 19:19:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFC PATCH v3 05/10] hw/arm/smmuv3: Parse STE config for stage-2 Content-Language: en-US To: Mostafa Saleh Cc: qemu-devel@nongnu.org, jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org References: <20230401104953.1325983-1-smostafa@google.com> <20230401104953.1325983-6-smostafa@google.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.666, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mostafa, On 5/15/23 17:37, Mostafa Saleh wrote: > Hi Eric, > > Thanks a lot for taking the time to review the patches. > > On Mon, May 15, 2023 at 03:03:28PM +0200, Eric Auger wrote: >>> >>> +/* If stage-1 fault enabled and ptw event targets it. */ >>> +#define PTW_FAULT_S1(cfg, event) ((cfg)->record_faults && \ >>> + !(event).u.f_walk_eabt.s2) >>> +/* If stage-2 fault enabled and ptw event targets it. */ >>> +#define PTW_FAULT_S2(cfg, event) ((cfg)->s2cfg.record_faults && \ >>> + (event).u.f_walk_eabt.s2) >>> + >>> +#define PTW_FAULT_ALLOWED(cfg, event) (PTW_FAULT_S1(cfg, event) || \ >>> + PTW_FAULT_S2(cfg, event)) >> The name of the macro does not really reflect what it tests. I would >> suggest PTW_RECORD_FAULT and PTW_RECORD_S1|S2_FAULT >> I would also suggest (cfg->stage == 1) ?  PTW_RECORD_S1_FAULT(cfg, >> event) :  PTW_RECORD_S2_FAULT(cfg, event) >> >> PTW_FAULT_S1() and PTW_FAULT_S2() are not used anywhere else. >> >> I would simplify PTW_RECORD_FAULT(cfg)  (cfg->stage == 1) ? >> (cfg)->record_faults:  (cfg)->s2cfg.record_faults > Yes, this is much simpler. > I am wondering as stage-2 only SMMUs can have stage-1 faults as described in > (IHI 0070.E.a) "3.4 Address sizes". > If the input address of a transaction exceeds the size of the IAS. > I guess this means that the fault record in this case is still controlled by S2R > although it is stage-1 fault as there is no CD or stage-1 config. Yes this sounds sensible. Eric > > Thanks, > Mostafa >