From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Robert Henry <robhenry@microsoft.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
"qemu-discuss@nongnu.org" <qemu-discuss@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>
Subject: Re: Emulating graviton G3
Date: Fri, 3 Mar 2023 10:36:03 +0100 [thread overview]
Message-ID: <3958a606-1e36-9a66-0ea0-ef2bc9749fb4@linaro.org> (raw)
In-Reply-To: <DM6PR21MB1497F02E1C66D07A066B1D63D6B39@DM6PR21MB1497.namprd21.prod.outlook.com>
Cc'ing qemu-arm@ list
On 3/3/23 08:20, Robert Henry wrote:
> I cannot figure out how to make QEMU TCG emulate aarch64 Graviton G3.
> I'm working against master/head of the QEMU source.
>
> I come up with feature names by consulting
> https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html
> <https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html> which
> is compendium of the /proc/cpuinfo info crowd sourced from linux running
> on real systems
>
> I'm trying to either (a) add features to QEMU's '-cpu neoverse-n1,...'
> or (b) take features away from '-cpu max,...'
>
> Unfortunately, many names of implemented or unimplemented features are
> not known by the -cpu mechanism. For example, from max I want to kill
> "smeb16f32", or from neoverse-n1 I want to add in "svei8mm", but neither
> name is known. Indeed, the only names known by -cpu are those exposed
> via the qmp mechanism are of the form "sveNNN" for vector bit width NNN.
>
> Is there some trick I'm missing?
parent reply other threads:[~2023-03-03 9:37 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <DM6PR21MB1497F02E1C66D07A066B1D63D6B39@DM6PR21MB1497.namprd21.prod.outlook.com>]
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