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From: Hollis Blanchard <hollisb@us.ibm.com>
To: qemu-devel@nongnu.org
Cc: l_indien@magic.fr, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 2 of 4] [qemu ppc uic] Remove interrupt polarity code
Date: Wed, 23 Apr 2008 17:23:53 -0500	[thread overview]
Message-ID: <39a9e699b6d6ca826b1a.1208989433@localhost.localdomain> (raw)
In-Reply-To: <patchbomb.1208989431@localhost.localdomain>

Interrupt polarity should have no functional effect, since qemu tracks logical
IRQ state, not the electrical state of physical lines.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>

diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -377,10 +377,7 @@
     if (irq_num < 0 || irq_num > 31)
         return;
     sr = uic->uicsr;
-    if (!(uic->uicpr & mask)) {
-        /* Negatively asserted IRQ */
-        level = level == 0 ? 1 : 0;
-    }
+
     /* Update status register */
     if (uic->uictr & mask) {
         /* Edge sensitive interrupt */
@@ -479,7 +476,6 @@
         break;
     case DCR_UICPR:
         uic->uicpr = val;
-        ppcuic_trigger_irq(uic);
         break;
     case DCR_UICTR:
         uic->uictr = val;

  parent reply	other threads:[~2008-04-23 22:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-04-23 22:23 [Qemu-devel] [PATCH 0 of 4] PowerPC 4xx device emulation improvements Hollis Blanchard
2008-04-23 22:23 ` [Qemu-devel] [PATCH 1 of 4] [qemu ppc uic] Order IRQ bit numbers as described in the UIC documentation Hollis Blanchard
2008-04-23 22:23 ` Hollis Blanchard [this message]
2008-04-23 22:23 ` [Qemu-devel] [PATCH 3 of 4] [qemu ppc uic] Remember the state of level-triggered interrupts Hollis Blanchard
2008-04-23 22:23 ` [Qemu-devel] [PATCH 4 of 4] [qemu ppc pci] Emulate the PCI(-legacy) controller found on some 440 SoCs Hollis Blanchard
2008-05-05  3:46   ` Aurelien Jarno

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