* [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function
@ 2022-03-15 7:57 Steven Lee
2022-03-15 7:57 ` [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and " Steven Lee
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Steven Lee @ 2022-03-15 7:57 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
AST2600's HPLL register offset and bit definition are different from AST2500.
The patch series adds a hpll calculation function for ast2600 and modify apb frequency
calculation function based on SCU200 register description and note in ast2600v11.pdf.
Changes since v1:
- introduce ast2400 and ast2600 get_apb_freq class handlers.
- introduce clkin_25Mhz attribute.
Please help to review.
Thanks,
Steven
Steven Lee (2):
hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
hw: aspeed_scu: Introduce clkin_25Mhz attribute
hw/misc/aspeed_scu.c | 45 ++++++++++++++++++++++++++++++++++--
include/hw/misc/aspeed_scu.h | 19 +++++++++++++++
2 files changed, 62 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
2022-03-15 7:57 [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Steven Lee
@ 2022-03-15 7:57 ` Steven Lee
2022-03-15 8:45 ` Cédric Le Goater
2022-03-15 7:57 ` [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute Steven Lee
2022-03-15 8:59 ` [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Cédric Le Goater
2 siblings, 1 reply; 6+ messages in thread
From: Steven Lee @ 2022-03-15 7:57 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function and an apb frequency calculation
function based on SCU200 register description in ast2600v11.pdf.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 39 +++++++++++++++++++++++++++++++++++-
include/hw/misc/aspeed_scu.h | 18 +++++++++++++++++
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index d06e179a6e..d65f86df3d 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -213,6 +213,11 @@ static uint32_t aspeed_scu_get_random(void)
}
uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
+{
+ return ASPEED_SCU_GET_CLASS(s)->get_apb(s);
+}
+
+static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s)
{
AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
@@ -221,6 +226,15 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
/ asc->apb_divider;
}
+static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s)
+{
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]);
+
+ return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1)
+ / asc->apb_divider;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -426,6 +440,26 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
return clkin * multiplier;
}
+static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
+{
+ uint32_t multiplier = 1;
+ uint32_t clkin = aspeed_scu_get_clkin(s);
+
+ if (hpll_reg & SCU_AST2600_H_PLL_OFF) {
+ return 0;
+ }
+
+ if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) {
+ uint32_t p = (hpll_reg >> 19) & 0xf;
+ uint32_t n = (hpll_reg >> 13) & 0x3f;
+ uint32_t m = hpll_reg & 0x1fff;
+
+ multiplier = ((m + 1) / (n + 1)) / (p + 1);
+ }
+
+ return clkin * multiplier;
+}
+
static void aspeed_scu_reset(DeviceState *dev)
{
AspeedSCUState *s = ASPEED_SCU(dev);
@@ -525,6 +559,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2400 System Control Unit";
asc->resets = ast2400_a0_resets;
asc->calc_hpll = aspeed_2400_scu_calc_hpll;
+ asc->get_apb = aspeed_2400_scu_get_apb_freq;
asc->apb_divider = 2;
asc->nr_regs = ASPEED_SCU_NR_REGS;
asc->ops = &aspeed_ast2400_scu_ops;
@@ -545,6 +580,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2500 System Control Unit";
asc->resets = ast2500_a1_resets;
asc->calc_hpll = aspeed_2500_scu_calc_hpll;
+ asc->get_apb = aspeed_2400_scu_get_apb_freq;
asc->apb_divider = 4;
asc->nr_regs = ASPEED_SCU_NR_REGS;
asc->ops = &aspeed_ast2500_scu_ops;
@@ -716,7 +752,8 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2600 System Control Unit";
dc->reset = aspeed_ast2600_scu_reset;
asc->resets = ast2600_a3_resets;
- asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;
+ asc->get_apb = aspeed_2600_scu_get_apb_freq;
asc->apb_divider = 4;
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
asc->ops = &aspeed_ast2600_scu_ops;
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index c14aff2bcb..6bf67589e8 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -56,6 +56,7 @@ struct AspeedSCUClass {
const uint32_t *resets;
uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
+ uint32_t (*get_apb)(AspeedSCUState *s);
uint32_t apb_divider;
uint32_t nr_regs;
const MemoryRegionOps *ops;
@@ -316,4 +317,21 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2500_HW_STRAP_RESERVED1)
+/* SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC)
+ *
+ * 28:26 H-PLL Parameters
+ * 25 Enable H-PLL reset
+ * 24 Enable H-PLL bypass mode
+ * 23 Turn off H-PLL
+ * 22:19 H-PLL Post Divider (P)
+ * 18:13 H-PLL Numerator (M)
+ * 12:0 H-PLL Denumerator (N)
+ *
+ * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
+ *
+ * The default frequency is 1200Mhz when CLKIN = 25MHz
+ */
+#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
+#define SCU_AST2600_H_PLL_OFF (0x1 << 23)
+
#endif /* ASPEED_SCU_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute
2022-03-15 7:57 [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Steven Lee
2022-03-15 7:57 ` [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and " Steven Lee
@ 2022-03-15 7:57 ` Steven Lee
2022-03-15 8:46 ` Cédric Le Goater
2022-03-15 8:59 ` [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Cédric Le Goater
2 siblings, 1 reply; 6+ messages in thread
From: Steven Lee @ 2022-03-15 7:57 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, steven_lee
AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute
for aspeed_scu_get_clkin() to return the correct clkin for ast2600.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 6 +++++-
include/hw/misc/aspeed_scu.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index d65f86df3d..150567f98a 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -371,7 +371,8 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops = {
static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
{
- if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
+ if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN ||
+ ASPEED_SCU_GET_CLASS(s)->clkin_25Mhz) {
return 25000000;
} else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
return 48000000;
@@ -562,6 +563,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
asc->get_apb = aspeed_2400_scu_get_apb_freq;
asc->apb_divider = 2;
asc->nr_regs = ASPEED_SCU_NR_REGS;
+ asc->clkin_25Mhz = false;
asc->ops = &aspeed_ast2400_scu_ops;
}
@@ -583,6 +585,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
asc->get_apb = aspeed_2400_scu_get_apb_freq;
asc->apb_divider = 4;
asc->nr_regs = ASPEED_SCU_NR_REGS;
+ asc->clkin_25Mhz = false;
asc->ops = &aspeed_ast2500_scu_ops;
}
@@ -756,6 +759,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
asc->get_apb = aspeed_2600_scu_get_apb_freq;
asc->apb_divider = 4;
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
+ asc->clkin_25Mhz = true;
asc->ops = &aspeed_ast2600_scu_ops;
}
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 6bf67589e8..fdc721846c 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -59,6 +59,7 @@ struct AspeedSCUClass {
uint32_t (*get_apb)(AspeedSCUState *s);
uint32_t apb_divider;
uint32_t nr_regs;
+ bool clkin_25Mhz;
const MemoryRegionOps *ops;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
2022-03-15 7:57 ` [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and " Steven Lee
@ 2022-03-15 8:45 ` Cédric Le Goater
0 siblings, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2022-03-15 8:45 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here
Cc: troy_lee, jamin_lin
On 3/15/22 08:57, Steven Lee wrote:
> AST2600's HPLL register offset and bit definition are different from
> AST2500. Add a hpll calculation function and an apb frequency calculation
> function based on SCU200 register description in ast2600v11.pdf.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/misc/aspeed_scu.c | 39 +++++++++++++++++++++++++++++++++++-
> include/hw/misc/aspeed_scu.h | 18 +++++++++++++++++
> 2 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index d06e179a6e..d65f86df3d 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -213,6 +213,11 @@ static uint32_t aspeed_scu_get_random(void)
> }
>
> uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
> +{
> + return ASPEED_SCU_GET_CLASS(s)->get_apb(s);
> +}
> +
> +static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s)
> {
> AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
> uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]);
> @@ -221,6 +226,15 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s)
> / asc->apb_divider;
> }
>
> +static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s)
> +{
> + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
> + uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]);
> +
> + return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1)
> + / asc->apb_divider;
> +}
> +
> static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
> {
> AspeedSCUState *s = ASPEED_SCU(opaque);
> @@ -426,6 +440,26 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
> return clkin * multiplier;
> }
>
> +static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
> +{
> + uint32_t multiplier = 1;
> + uint32_t clkin = aspeed_scu_get_clkin(s);
> +
> + if (hpll_reg & SCU_AST2600_H_PLL_OFF) {
> + return 0;
> + }
> +
> + if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) {
> + uint32_t p = (hpll_reg >> 19) & 0xf;
> + uint32_t n = (hpll_reg >> 13) & 0x3f;
> + uint32_t m = hpll_reg & 0x1fff;
> +
> + multiplier = ((m + 1) / (n + 1)) / (p + 1);
> + }
> +
> + return clkin * multiplier;
> +}
> +
> static void aspeed_scu_reset(DeviceState *dev)
> {
> AspeedSCUState *s = ASPEED_SCU(dev);
> @@ -525,6 +559,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
> dc->desc = "ASPEED 2400 System Control Unit";
> asc->resets = ast2400_a0_resets;
> asc->calc_hpll = aspeed_2400_scu_calc_hpll;
> + asc->get_apb = aspeed_2400_scu_get_apb_freq;
> asc->apb_divider = 2;
> asc->nr_regs = ASPEED_SCU_NR_REGS;
> asc->ops = &aspeed_ast2400_scu_ops;
> @@ -545,6 +580,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
> dc->desc = "ASPEED 2500 System Control Unit";
> asc->resets = ast2500_a1_resets;
> asc->calc_hpll = aspeed_2500_scu_calc_hpll;
> + asc->get_apb = aspeed_2400_scu_get_apb_freq;
> asc->apb_divider = 4;
> asc->nr_regs = ASPEED_SCU_NR_REGS;
> asc->ops = &aspeed_ast2500_scu_ops;
> @@ -716,7 +752,8 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
> dc->desc = "ASPEED 2600 System Control Unit";
> dc->reset = aspeed_ast2600_scu_reset;
> asc->resets = ast2600_a3_resets;
> - asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
> + asc->calc_hpll = aspeed_2600_scu_calc_hpll;
> + asc->get_apb = aspeed_2600_scu_get_apb_freq;
> asc->apb_divider = 4;
> asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
> asc->ops = &aspeed_ast2600_scu_ops;
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index c14aff2bcb..6bf67589e8 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -56,6 +56,7 @@ struct AspeedSCUClass {
>
> const uint32_t *resets;
> uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
> + uint32_t (*get_apb)(AspeedSCUState *s);
> uint32_t apb_divider;
> uint32_t nr_regs;
> const MemoryRegionOps *ops;
> @@ -316,4 +317,21 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
> SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
> SCU_AST2500_HW_STRAP_RESERVED1)
>
> +/* SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC)
> + *
> + * 28:26 H-PLL Parameters
> + * 25 Enable H-PLL reset
> + * 24 Enable H-PLL bypass mode
> + * 23 Turn off H-PLL
> + * 22:19 H-PLL Post Divider (P)
> + * 18:13 H-PLL Numerator (M)
> + * 12:0 H-PLL Denumerator (N)
> + *
> + * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
> + *
> + * The default frequency is 1200Mhz when CLKIN = 25MHz
> + */
> +#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
> +#define SCU_AST2600_H_PLL_OFF (0x1 << 23)
> +
> #endif /* ASPEED_SCU_H */
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute
2022-03-15 7:57 ` [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute Steven Lee
@ 2022-03-15 8:46 ` Cédric Le Goater
0 siblings, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2022-03-15 8:46 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here
Cc: troy_lee, jamin_lin
On 3/15/22 08:57, Steven Lee wrote:
> AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute
> for aspeed_scu_get_clkin() to return the correct clkin for ast2600.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/misc/aspeed_scu.c | 6 +++++-
> include/hw/misc/aspeed_scu.h | 1 +
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index d65f86df3d..150567f98a 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -371,7 +371,8 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops = {
>
> static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
> {
> - if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
> + if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN ||
> + ASPEED_SCU_GET_CLASS(s)->clkin_25Mhz) {
> return 25000000;
> } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
> return 48000000;
> @@ -562,6 +563,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
> asc->get_apb = aspeed_2400_scu_get_apb_freq;
> asc->apb_divider = 2;
> asc->nr_regs = ASPEED_SCU_NR_REGS;
> + asc->clkin_25Mhz = false;
> asc->ops = &aspeed_ast2400_scu_ops;
> }
>
> @@ -583,6 +585,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
> asc->get_apb = aspeed_2400_scu_get_apb_freq;
> asc->apb_divider = 4;
> asc->nr_regs = ASPEED_SCU_NR_REGS;
> + asc->clkin_25Mhz = false;
> asc->ops = &aspeed_ast2500_scu_ops;
> }
>
> @@ -756,6 +759,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
> asc->get_apb = aspeed_2600_scu_get_apb_freq;
> asc->apb_divider = 4;
> asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
> + asc->clkin_25Mhz = true;
> asc->ops = &aspeed_ast2600_scu_ops;
> }
>
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index 6bf67589e8..fdc721846c 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -59,6 +59,7 @@ struct AspeedSCUClass {
> uint32_t (*get_apb)(AspeedSCUState *s);
> uint32_t apb_divider;
> uint32_t nr_regs;
> + bool clkin_25Mhz;
> const MemoryRegionOps *ops;
> };
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function
2022-03-15 7:57 [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Steven Lee
2022-03-15 7:57 ` [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and " Steven Lee
2022-03-15 7:57 ` [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute Steven Lee
@ 2022-03-15 8:59 ` Cédric Le Goater
2 siblings, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2022-03-15 8:59 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here
Cc: troy_lee, jamin_lin
On 3/15/22 08:57, Steven Lee wrote:
> AST2600's HPLL register offset and bit definition are different from AST2500.
> The patch series adds a hpll calculation function for ast2600 and modify apb frequency
> calculation function based on SCU200 register description and note in ast2600v11.pdf.
>
> Changes since v1:
> - introduce ast2400 and ast2600 get_apb_freq class handlers.
> - introduce clkin_25Mhz attribute.
>
Looks good. They are queued for QEMU 7.1.
Something I never had time to look at is the clock hierarchy in QEMU
Aspeed machines :
https://qemu.readthedocs.io/en/latest/devel/clocks.html
It would be very useful to start the tree with clkin and the obvious
derived clocks.
Thanks,
C.
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
fsiclk-gate 1 1 0 0 0 0 50000 Y
i3cclk-gate 0 0 0 0 0 0 50000 N
emmcclk-gate 1 1 0 0 0 0 50000 Y
sdclk-gate 1 1 0 0 0 0 50000 Y
rvasclk-gate 0 0 0 0 0 0 50000 N
rsaclk-gate 0 0 0 0 0 0 50000 N
usb-port2-gate 1 1 0 0 0 0 50000 Y
usb-port1-gate 1 1 0 0 0 0 50000 Y
usb-uhci-gate 1 1 0 0 0 0 50000 Y
espiclk-gate 0 0 0 0 0 0 50000 N
yclk-gate 0 0 0 0 0 0 50000 N
lclk-gate 0 0 0 0 0 0 50000 N
dclk-gate 1 1 0 0 0 0 50000 Y
vclk-gate 0 0 0 0 0 0 50000 N
gclk-gate 0 0 0 0 0 0 50000 N
eclk 0 0 0 0 0 0 50000 Y
eclk-gate 0 0 0 0 0 0 50000 N
uartx 0 0 0 1846153 0 0 50000 Y
uart13clk-gate 0 0 0 1846153 0 0 50000 N
uart12clk-gate 0 0 0 1846153 0 0 50000 N
uart11clk-gate 0 0 0 1846153 0 0 50000 N
uart10clk-gate 0 0 0 1846153 0 0 50000 N
uart9clk-gate 0 0 0 1846153 0 0 50000 N
uart8clk-gate 0 0 0 1846153 0 0 50000 N
uart7clk-gate 0 0 0 1846153 0 0 50000 N
uart6clk-gate 0 0 0 1846153 0 0 50000 N
uart 1 1 0 24000000 0 0 50000 Y
uart5clk-gate 1 1 0 24000000 0 0 50000 Y
uart4clk-gate 0 0 0 24000000 0 0 50000 N
uart3clk-gate 0 0 0 24000000 0 0 50000 N
uart2clk-gate 0 0 0 24000000 0 0 50000 N
uart1clk-gate 0 0 0 24000000 0 0 50000 N
usb-phy-40m 0 0 0 40000000 0 0 50000 Y
clkin 4 4 0 25000000 0 0 50000 Y
ref1clk-gate 1 1 0 25000000 0 0 50000 Y
ref0clk-gate 1 1 0 25000000 0 0 50000 Y
apll 0 0 0 800000000 0 0 50000 Y
epll 0 0 0 1000000000 0 0 50000 Y
dpll 0 0 0 50000000 0 0 50000 Y
vclk 0 0 0 50000000 0 0 50000 Y
mpll 2 2 0 400000000 0 0 50000 Y
mclk-gate 1 1 0 400000000 0 0 50000 Y
emmc_extclk_mux 1 1 0 400000000 0 0 50000 Y
emmc_extclk_gate 1 1 0 400000000 0 0 50000 Y
emmc_extclk 1 1 0 200000000 0 0 50000 Y
hpll 4 4 0 1200000000 0 0 50000 Y
bclk 1 1 0 150000000 0 0 50000 Y
bclk-gate 1 1 0 150000000 0 0 50000 Y
lhclk 0 0 0 150000000 0 0 50000 Y
lhclk-gate 0 0 0 150000000 0 0 50000 N
mac34 2 2 0 300000000 0 0 50000 Y
mac4clk-gate 1 1 0 300000000 0 0 50000 Y
mac3clk-gate 1 1 0 300000000 0 0 50000 Y
mac12 2 2 0 200000000 0 0 50000 Y
mac2clk-gate 1 1 0 200000000 0 0 50000 Y
mac1clk-gate 1 1 0 200000000 0 0 50000 Y
mac12rclk 0 0 0 50000000 0 0 50000 Y
mac2rclk 0 0 0 50000000 0 0 50000 N
mac1rclk 0 0 0 50000000 0 0 50000 N
sd_extclk_gate 0 0 0 1200000000 0 0 50000 N
sd_extclk 0 0 0 150000000 0 0 50000 Y
emmc_extclk_hpll_in 0 0 0 600000000 0 0 50000 Y
apb1 0 0 0 37500000 0 0 50000 Y
ahb 3 3 0 200000000 0 0 50000 Y
i3cclk 0 0 0 200000000 0 0 50000 Y
i3c6clk-gate 0 0 0 200000000 0 0 50000 N
i3c5clk-gate 0 0 0 200000000 0 0 50000 N
i3c4clk-gate 0 0 0 200000000 0 0 50000 N
i3c3clk-gate 0 0 0 200000000 0 0 50000 N
i3c2clk-gate 0 0 0 200000000 0 0 50000 N
i3c1clk-gate 0 0 0 200000000 0 0 50000 N
i3c0clk-gate 0 0 0 200000000 0 0 50000 N
apb2 0 0 0 100000000 0 0 50000 Y
d1clk 0 0 0 0 0 0 50000 Y
d1clk-gate 0 0 0 0 0 0 50000 N
mac34rclk 0 0 0 0 0 0 50000 Y
mac4rclk 0 0 0 50000000 0 0 50000 N
mac3rclk 0 0 0 50000000 0 0 50000 N
^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-03-15 7:57 [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Steven Lee
2022-03-15 7:57 ` [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and " Steven Lee
2022-03-15 8:45 ` Cédric Le Goater
2022-03-15 7:57 ` [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute Steven Lee
2022-03-15 8:46 ` Cédric Le Goater
2022-03-15 8:59 ` [PATCH v2 0/2] hw: aspeed_scu: Add AST2600 hpll calculation function Cédric Le Goater
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