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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce5e83e1sm4717821f8f.51.2025.10.10.08.05.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Oct 2025 08:05:47 -0700 (PDT) Message-ID: <39bc0cef-cda7-43f7-8d9c-870599a6e91d@linaro.org> Date: Fri, 10 Oct 2025 17:05:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 09/18] target/riscv: accessors to registers upper part and 128-bit load/store Content-Language: en-US To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, fabien.portas@grenoble-inp.org, alistair.francis@wdc.com References: <20220106210108.138226-1-frederic.petrot@univ-grenoble-alpes.fr> <20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Frédéric, (old patch merged as commit a2f827ff4f44) On 6/1/22 22:00, Frédéric Pétrot wrote: > Get function to retrieve the 64 top bits of a register, stored in the gprh > field of the cpu state. Set function that writes the 128-bit value at once. > The access to the gprh field can not be protected at compile time to make > sure it is accessed only in the 128-bit version of the processor because we > have no way to indicate that the misa_mxl_max field is const. > > The 128-bit ISA adds ldu, lq and sq. We provide support for these > instructions. Note that (a) we compute only 64-bit addresses to actually > access memory, cowardly utilizing the existing address translation mechanism > of QEMU, and (b) we assume for now little-endian memory accesses. > > Signed-off-by: Frédéric Pétrot > Co-authored-by: Fabien Portas > Reviewed-by: Alistair Francis > --- > target/riscv/insn16.decode | 27 ++++++- > target/riscv/insn32.decode | 5 ++ > target/riscv/translate.c | 41 ++++++++++ > target/riscv/insn_trans/trans_rvi.c.inc | 100 ++++++++++++++++++++++-- > 4 files changed, 163 insertions(+), 10 deletions(-) > +/* Compute only 64-bit addresses to use the address translation mechanism */ > +static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) > +{ > + TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv destl = dest_gpr(ctx, a->rd); > + TCGv desth = dest_gprh(ctx, a->rd); > + TCGv addrl = tcg_temp_new(); > + > + tcg_gen_addi_tl(addrl, src1l, a->imm); > + > + if ((memop & MO_SIZE) <= MO_64) { > + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop); > + if (memop & MO_SIGN) { > + tcg_gen_sari_tl(desth, destl, 63); > + } else { > + tcg_gen_movi_tl(desth, 0); > + } > + } else { > + /* assume little-endian memory access for now */ > + tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); > + tcg_gen_addi_tl(addrl, addrl, 8); > + tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); I am confused by this "assume little-endian access" comment, since you set the MO_TE flag (target endianness). I suppose you added the comment since the @memop argument is ignored in this code path. Maybe you want 'MO_LEUQ' here instead, to select little endianness? > + } > + > + gen_set_gpr128(ctx, a->rd, destl, desth); > + > + tcg_temp_free(addrl); > + return true; > +} > + > +static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) > +{ > + if (get_xl(ctx) == MXL_RV128) { > + return gen_load_i128(ctx, a, memop); > + } else { > + return gen_load_tl(ctx, a, memop); > + } > +}