From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH for-10.1 08/10] target/arm: Don't nest H() macro calls in SVE DO_REDUCE
Date: Fri, 18 Jul 2025 14:44:10 -0700 [thread overview]
Message-ID: <39d4bf8d-d5d5-4500-b819-628e70ff3470@linaro.org> (raw)
In-Reply-To: <20250718173032.2498900-9-peter.maydell@linaro.org>
On 7/18/25 10:30, Peter Maydell wrote:
> In the part of the SVE DO_REDUCE macro used by the SVE2p1 FMAXQV,
> FMINQV, etc insns, we incorrectly applied the H() macro twice when
> calculating an offset to add to the vn pointer. This has no effect
> on little-endian hosts but on big-endian hosts the two invocations
> will cancel each other out and we will access the wrong part of the
> array.
>
> The "s * 16" part of the expression is already aligned, so we only
> need to use the H macro on the "e". Correct the macro usage.
>
> Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/tcg/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
> index 105cc5dd122..bf894f0bf13 100644
> --- a/target/arm/tcg/sve_helper.c
> +++ b/target/arm/tcg/sve_helper.c
> @@ -4509,7 +4509,7 @@ void helper_sve2p1_##NAME##qv_##SUF(void *vd, void *vn, void *vg, \
> TYPE data[ARM_MAX_VQ]; \
> for (unsigned s = 0; s < segments; s++) { \
> uint16_t pg = *(uint16_t *)(vg + H1_2(s * 2)); \
> - TYPE nn = *(TYPE *)(vn + H(s * 16 + H(e))); \
> + TYPE nn = *(TYPE *)(vn + (s * 16 + H(e))); \
> data[s] = (pg >> e) & 1 ? nn : IDENT; \
> } \
> *(TYPE *)(vd + H(e)) = FUNC##_reduce(data, status, segments); \
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-07-18 22:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-18 17:30 [PATCH for-10.1 00/10] target/arm: Some SVE2p1 fixes Peter Maydell
2025-07-18 17:30 ` [PATCH for-10.1 01/10] target/arm: Add BFADD, BFSUB, BFMUL (unpredicated) Peter Maydell
2025-07-18 21:29 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 02/10] target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated) Peter Maydell
2025-07-18 21:32 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 03/10] target/arm: Add BFMIN, BFMAX (predicated) Peter Maydell
2025-07-18 21:34 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 04/10] target/arm: Add BFMUL (indexed) Peter Maydell
2025-07-18 21:38 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 05/10] target/arm: Add BFMLA, BFMLS (vectors) Peter Maydell
2025-07-18 21:40 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 06/10] target/arm: Add BFMLA, BFMLS (indexed) Peter Maydell
2025-07-18 21:42 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 07/10] target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV Peter Maydell
2025-07-18 21:43 ` Richard Henderson
2025-07-21 8:21 ` Philippe Mathieu-Daudé
2025-07-18 17:30 ` [PATCH for-10.1 08/10] target/arm: Don't nest H() macro calls in SVE DO_REDUCE Peter Maydell
2025-07-18 21:44 ` Richard Henderson [this message]
2025-07-18 17:30 ` [PATCH for-10.1 09/10] target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV Peter Maydell
2025-07-18 21:45 ` Richard Henderson
2025-07-18 17:30 ` [PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u Peter Maydell
2025-07-18 21:46 ` Richard Henderson
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