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Wed, 14 Oct 2020 12:21:08 +0200 (CEST) Received: from [148.251.23.173] (ml.mymailcheap.com [148.251.23.173]) by mail20.mymailcheap.com (Postfix) with ESMTP id 9150E41C2B; Wed, 14 Oct 2020 10:21:07 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=@flygoat.com header.b="T6rMlNc6"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from [0.0.0.0] (unknown [146.196.55.70]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 04B0E41C28; Wed, 14 Oct 2020 10:20:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1602670857; bh=UeaN1nzl6zUGv/G7CSDK+RLxzRYtapQFLLrqETJ/xoE=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=T6rMlNc6E/nfys38hgKrkoczpyRBclKupNdlB53CrtopR/qD3m24rneE/uf6wwYaq mBNJ8ohN5N67eg/fHuxqkD6odWSCT8K2ER7FLLaj9CWr16RrQncuwrEulgAbvgopVh 0dS8CpYF0YkxuSGD6LmrHp8GvG6dDlQ7zx0ESzQ4= Subject: Re: [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU property To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, Victor Kamensky References: <20201013132535.3599453-1-f4bug@amsat.org> <20201013132535.3599453-4-f4bug@amsat.org> From: Jiaxun Yang Message-ID: <39e98c46-d22d-621e-c559-a6e31c5aad6c@flygoat.com> Date: Wed, 14 Oct 2020 18:20:49 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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SUSPICIOUS_RECIPS(1.50)[]; RCVD_COUNT_TWO(0.00)[2] X-Rspamd-Server: mail20.mymailcheap.com Received-SPF: pass client-ip=144.217.248.100; envelope-from=jiaxun.yang@flygoat.com; helo=relay1.mymailcheap.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/14 06:21:12 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Khem Raj , Aleksandar Markovic , Richard Purdie , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" 在 2020/10/13 21:25, Philippe Mathieu-Daudé 写道: > Allow changing the number of TLB entries for > testing/tunning purpose. > > Example to force a 34Kf cpu with 64 TLB: > > $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ... > > This is helpful for developers of the Yocto Project [*]: > > Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit > MIPS CI loop. It was observed that in this case CI test execution > time was almost twice longer than 64bit MIPS variant that runs > under MIPS64R2-generic model. It was investigated and concluded > that the difference in number of TLBs 16 in 34Kf case vs 64 in > MIPS64R2-generic is responsible for most of CI real time execution > difference. Because with 16 TLBs linux user-land trashes TLB more > and it needs to execute more instructions in TLB refill handler > calls, as result it runs much longer. > > [*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html > > Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 > Reported-by: Victor Kamensky > Signed-off-by: Philippe Mathieu-Daudé > --- Hi Philippe, I think name can this property vtlb-entries? MIPS R2 had introduced dual-TLB feature and the entries specified here is the number of VTLB, while FTLB is another set of entries with fixed pagesize. Although MIPS TCG haven't implemented dual-TLB but it can prevent future confusion. Thanks. - Jiaxun