From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Richard Henderson <richard.henderson@linaro.org>,
sagark@eecs.berkeley.edu, palmer@sifive.com,
Alistair.Francis@wdc.com
Cc: peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding
Date: Tue, 22 Jan 2019 10:00:53 +0100 [thread overview]
Message-ID: <3a9e0117-d2d9-39d9-4935-9a6da88efe5f@mail.uni-paderborn.de> (raw)
In-Reply-To: <3da52a06-911a-5459-021c-526b23d9a928@linaro.org>
On 1/22/19 12:22 AM, Richard Henderson wrote:
> On 1/21/19 1:10 AM, Bastian Koppelmann wrote:
>> On 1/20/19 2:43 AM, Richard Henderson wrote:
>>> On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
>>>> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>>>> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
>>>> ---
>>>> v3 -> v4:
>>>> - refactor tcg_gen_set_cond_tl(TCG_COND_LT,..) into gen_slt function
>>>> and reuse gen_arith(..., &gen_slt) for all trans_slt functions.
>>>> - Add missing sign extension to trans_srlw/sllw
>>>> - Made rs2 == 0 a special case of srlw/sllw
>>> Why? It's not like it is a likely case, and it works without.
>>
>> Because you suggested it :) (see https://patchwork.kernel.org/patch/10662699/).
>> Maybe I misunderstood your comment. If you like I can remove it in the respin.
> I meant the register indicated by rs2 containing the value 0,
> which you have fixed with the extension.
I see. I remove it in the respin.
Cheers,
Bastian
next prev parent reply other threads:[~2019-01-22 9:01 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 13:14 [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-19 21:20 ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-19 21:29 ` Richard Henderson
2019-01-21 9:05 ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-19 21:51 ` Richard Henderson
2019-01-21 9:06 ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-19 21:56 ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-20 1:24 ` Richard Henderson
2019-01-21 9:07 ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-20 1:43 ` Richard Henderson
2019-01-21 9:10 ` Bastian Koppelmann
2019-01-21 23:22 ` Richard Henderson
2019-01-22 9:00 ` Bastian Koppelmann [this message]
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-20 1:48 ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste> Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-31 17:59 ` [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree no-reply
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