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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id q10-20020a056a00088a00b004f7ceff389esm31471726pfj.152.2022.04.09.12.20.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Apr 2022 12:20:32 -0700 (PDT) Message-ID: <3a9e2d33-8174-d480-50e4-4da0985bc486@linaro.org> Date: Sat, 9 Apr 2022 12:20:30 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 25/41] hw/intc/arm_gicv3_cpuif: Support vLPIs Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220408141550.1271295-1-peter.maydell@linaro.org> <20220408141550.1271295-26-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220408141550.1271295-26-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/8/22 07:15, Peter Maydell wrote: > The CPU interface changes to support vLPIs are fairly minor: > in the parts of the code that currently look at the list registers > to determine the highest priority pending virtual interrupt, we > must also look at the highest priority pending vLPI. To do this > we change hppvi_index() to check the vLPI and return a special-case > value if that is the right virtual interrupt to take. The callsites > (which handle HPPIR and IAR registers and the "raise vIRQ and vFIQ > lines" code) then have to handle this special-case value. > > This commit includes two interfaces with the as-yet-unwritten > redistributor code: > * the new GICv3CPUState::hppvlpi will be set by the redistributor > (in the same way as the existing hpplpi does for physical LPIs) > * when the CPU interface acknowledges a vLPI it needs to set it > to non-pending; the new gicv3_redist_vlpi_pending() function > (which matches the existing gicv3_redist_lpi_pending() used > for physical LPIs) is a stub that will be filled in later > > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson > @@ -2632,6 +2735,12 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) > GICv3CPUState *cs = opaque; > > gicv3_cpuif_update(cs); > + /* > + * Because vLPIs are only pending in NonSecure state, > + * an EL change can change the VIRQ/VFIQ status (but > + * cannot affect the maintenance interrupt state) > + */ > + gicv3_cpuif_virt_irq_fiq_update(cs); I'm a little bit surprised this is here, and not in arm_cpu_exec_interrupt (or a subroutine). Is this because if a virq has highest priority, we have to find the highest prio physical interrupt? r~