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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736984f6f82sm1910497b3a.115.2025.03.06.15.16.44 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Mar 2025 15:16:45 -0800 (PST) Message-ID: <3acf66e6-449d-4e39-b5e2-3b495cb5881b@linaro.org> Date: Thu, 6 Mar 2025 15:16:43 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/10] target/arm: Forbid return to AArch32 when CPU is AArch64-only To: qemu-devel@nongnu.org References: <20250306163925.2940297-1-peter.maydell@linaro.org> <20250306163925.2940297-11-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250306163925.2940297-11-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/6/25 08:39, Peter Maydell wrote: > In the Arm ARM, rule R_TYTWB states that returning to AArch32 > is an illegal exception return if: > * AArch32 is not supported at any exception level > * the target EL is configured for AArch64 via SCR_EL3.RW > or HCR_EL2.RW or via CPU state at reset > > We check the second of these, but not the first (which can only be > relevant for the case of a return to EL0, because if AArch32 is not > supported at one of the higher ELs then the RW bits will have an > effective value of 1 and the the "configured for AArch64" condition > will hold also). > > Add the missing condition. This isn't currently a bug because > all our CPUs support AArch32 at EL0, but future CPUs we add > might be 64-bit only. > > Signed-off-by: Peter Maydell > --- > target/arm/tcg/helper-a64.c | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Richard Henderson r~