* [PATCH] target/loongarch: Remove avail_64 in trans_srai_w()
@ 2024-06-17 13:07 Feiyang Chen
2024-06-17 18:09 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Feiyang Chen @ 2024-06-17 13:07 UTC (permalink / raw)
To: gaosong; +Cc: Feiyang Chen, c, qemu-devel
Since srai.w is a valid instruction on la32, simply remove the avail_64 check.
Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only instructions")
Signed-off-by: Feiyang Chen <chris.chenfeiyang@gmail.com>
---
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
index 2f4bd6ff28..8bcf341b22 100644
--- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
@@ -72,10 +72,6 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
- if (!avail_64(ctx)) {
- return false;
- }
-
tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
gen_set_gpr(a->rd, dest, EXT_NONE);
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/loongarch: Remove avail_64 in trans_srai_w()
2024-06-17 13:07 [PATCH] target/loongarch: Remove avail_64 in trans_srai_w() Feiyang Chen
@ 2024-06-17 18:09 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2024-06-17 18:09 UTC (permalink / raw)
To: Feiyang Chen, gaosong; +Cc: c, qemu-devel
On 6/17/24 06:07, Feiyang Chen wrote:
> Since srai.w is a valid instruction on la32, simply remove the avail_64 check.
>
> Fixes: c0c0461e3a06 ("target/loongarch: Add avail_64 to check la64-only instructions")
> Signed-off-by: Feiyang Chen <chris.chenfeiyang@gmail.com>
> ---
> target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> index 2f4bd6ff28..8bcf341b22 100644
> --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
> @@ -72,10 +72,6 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
> TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
>
> - if (!avail_64(ctx)) {
> - return false;
> - }
> -
> tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
> gen_set_gpr(a->rd, dest, EXT_NONE);
>
For the bug fix alone:
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
I'm not sure why this trans function is handled specially.
I think this would be better as
static void gen_sari_w(TCGv dest, TCGv src1, target_long imm)
{
tcg_gen_sextract_tl(dest, src1, imm, 32 - imm);
}
TRANS(sari_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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