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[2003:cb:c703:d900:a75d:cddc:d29f:bdb3]) by smtp.gmail.com with ESMTPSA id t18-20020a5d6912000000b0021d888e1132sm7533911wru.43.2022.07.12.00.14.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Jul 2022 00:14:07 -0700 (PDT) Message-ID: <3b0504e9-4adf-34e6-464f-37b4f11d48b0@redhat.com> Date: Tue, 12 Jul 2022 09:14:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/3] accel/tcg: Fix unaligned stores to s390x low-address-protected lowcore Content-Language: en-US To: Ilya Leoshkevich , Richard Henderson , Paolo Bonzini , Cornelia Huck , Thomas Huth , Halil Pasic , Christian Borntraeger , Eric Farman Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org References: <20220711185640.3558813-1-iii@linux.ibm.com> <20220711185640.3558813-2-iii@linux.ibm.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: <20220711185640.3558813-2-iii@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=david@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11.07.22 20:56, Ilya Leoshkevich wrote: > If low-address-protection is active, unaligned stores to non-protected > parts of lowcore lead to protection exceptions. The reason is that in > such cases tlb_fill() call in store_helper_unaligned() covers > [0, addr + size) range, which contains the protected portion of > lowcore. This range is too large. > > The most straightforward fix would be to make sure we stay within the > original [addr, addr + size) range. However, if an unaligned access > affects a single page, we don't need to call tlb_fill() in > store_helper_unaligned() at all, since it would be identical to > the previous tlb_fill() call in store_helper(), and therefore a no-op. > If an unaligned access covers multiple pages, this situation does not > occur. > > Therefore simply skip TLB handling in store_helper_unaligned() if we > are dealing with a single page. > > Fixes: 2bcf018340cb ("s390x/tcg: low-address protection support") > Signed-off-by: Ilya Leoshkevich > --- > accel/tcg/cputlb.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index f90f4312ea..a46f3a654d 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -2248,7 +2248,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, > const size_t tlb_off = offsetof(CPUTLBEntry, addr_write); > uintptr_t index, index2; > CPUTLBEntry *entry, *entry2; > - target_ulong page2, tlb_addr, tlb_addr2; > + target_ulong page1, page2, tlb_addr, tlb_addr2; > MemOpIdx oi; > size_t size2; > int i; > @@ -2256,15 +2256,17 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, > /* > * Ensure the second page is in the TLB. Note that the first page > * is already guaranteed to be filled, and that the second page > - * cannot evict the first. > + * cannot evict the first. An exception to this rule is PAGE_WRITE_INV > + * handling: the first page could have evicted itself. > */ > + page1 = addr & TARGET_PAGE_MASK; > page2 = (addr + size) & TARGET_PAGE_MASK; > size2 = (addr + size) & ~TARGET_PAGE_MASK; > index2 = tlb_index(env, mmu_idx, page2); > entry2 = tlb_entry(env, mmu_idx, page2); > > tlb_addr2 = tlb_addr_write(entry2); > - if (!tlb_hit_page(tlb_addr2, page2)) { > + if (page1 != page2 && !tlb_hit_page(tlb_addr2, page2)) { > if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { > tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, > mmu_idx, retaddr); Reviewed-by: David Hildenbrand -- Thanks, David / dhildenb