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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Richard Henderson <richard.henderson@linaro.org>,
	sagark@eecs.berkeley.edu, palmer@sifive.com,
	Alistair.Francis@wdc.com
Cc: peer.adelt@hni.uni-paderborn.de, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence insns to decodetree
Date: Mon, 21 Jan 2019 10:05:03 +0100	[thread overview]
Message-ID: <3b4cde8c-a403-db62-2c36-34691610fea2@mail.uni-paderborn.de> (raw)
In-Reply-To: <74f85a7c-62d1-ca61-9820-7c4deeca4a05@linaro.org>


On 1/19/19 10:29 PM, Richard Henderson wrote:
> On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
>> ---
>>   target/riscv/insn32.decode              |  2 ++
>>   target/riscv/insn_trans/trans_rvi.inc.c | 23 +++++++++++++++++++++++
>>   target/riscv/translate.c                | 12 ------------
>>   3 files changed, 25 insertions(+), 12 deletions(-)
>>
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 1f5bf1f6f9..804b721ca5 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -82,3 +82,5 @@ srl      0000000 .....    ..... 101 ..... 0110011 @r
>>   sra      0100000 .....    ..... 101 ..... 0110011 @r
>>   or       0000000 .....    ..... 110 ..... 0110011 @r
>>   and      0000000 .....    ..... 111 ..... 0110011 @r
>> +fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
>> +fence_i  ---- ----   ----   ----- 001 ----- 0001111
>> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
>> index 01f751650a..138a8397d9 100644
>> --- a/target/riscv/insn_trans/trans_rvi.inc.c
>> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
>> @@ -318,3 +318,26 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
>>       return true;
>>   }
>>   #endif
>> +
>> +static bool trans_fence(DisasContext *ctx, arg_fence *a)
>> +{
>> +#ifndef CONFIG_USER_ONLY
>> +    /* FENCE is a full memory barrier. */
>> +    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
>> +#endif
>> +    return true;
>> +}
>> +
>> +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>> +{
>> +#ifndef CONFIG_USER_ONLY
>> +    /*
>> +     * FENCE_I is a no-op in QEMU,
>> +     * however we need to end the translation block
>> +     */
>> +    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
>> +    tcg_gen_exit_tb(NULL, 0);
>> +    ctx->base.is_jmp = DISAS_NORETURN;
>> +#endif
>> +    return true;
> Rebase error.  You need to remove the ifdefs that were removed...


Whoops, I guess that's what you get, if you don't touch a patchset for 
some time ;)

  reply	other threads:[~2019-01-21  9:05 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-18 13:14 [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-19 21:20   ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-19 21:29   ` Richard Henderson
2019-01-21  9:05     ` Bastian Koppelmann [this message]
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-19 21:51   ` Richard Henderson
2019-01-21  9:06     ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-19 21:56   ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-20  1:24   ` Richard Henderson
2019-01-21  9:07     ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-20  1:43   ` Richard Henderson
2019-01-21  9:10     ` Bastian Koppelmann
2019-01-21 23:22       ` Richard Henderson
2019-01-22  9:00         ` Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-20  1:48   ` Richard Henderson
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste> Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-18 13:14 ` [Qemu-devel] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-31 17:59 ` [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree no-reply

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