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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: David Brenken <david.brenken@efs-auto.org>, qemu-devel@nongnu.org
Cc: Florian Artmeier <florian.artmeier@efs-auto.de>,
	David Brenken <david.brenken@efs-auto.de>,
	Georg Hofstetter <georg.hofstetter@efs-auto.de>
Subject: Re: [Qemu-devel] [PATCH 1/5] tricore: added some missing cpu instructions
Date: Tue, 20 Feb 2018 16:48:18 +0100	[thread overview]
Message-ID: <3b604800-0973-8c59-7d60-680bcc11ab4c@mail.uni-paderborn.de> (raw)
In-Reply-To: <20180219061827.2112-2-david.brenken@efs-auto.org>

On 02/19/2018 07:18 AM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
> 
> +    case OPC1_16_SBR_JEQ2:
> +        gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
> +                        offset + 16);
> +        break;

This is a 1.6+ instruction and you need to add a check, like with
OPC2_32_RR_MOVS_64.

>      case OPC1_16_SBR_JNE:
>          gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
>                          offset);
>          break;
> +    case OPC1_16_SBR_JNE2:
> +        gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
> +                        offset + 16);
> +        break;

Likewise.

>      case OPC1_16_SBR_JNZ:
>          gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
>          break;
> @@ -4089,6 +4097,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
>          gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
>          break;
>  /* SB-format */
> +    case OPC1_16_SB_JNE:
> +        address = MASK_OP_SBC_DISP4(ctx->opcode);
> +        gen_compute_branch(ctx, op1, 0, 0, 0, address);
> +        break;

Why duplicate the code here? First, OPC1_16_SB_JNE is the same opcode as
OPC1_16_SBR_JNE2. Second, you can just add your case below
OPC1_16_SBR_JNE in decode_16Bit_opc().

> @@ -321,11 +322,13 @@ enum {
>      OPC1_16_SBC_JNE                                  = 0x5e,
>      OPC1_16_SBC_JNE2                                 = 0xde,
>      OPC1_16_SBR_JNE                                  = 0x7e,
> +    OPC1_16_SBR_JNE2                                 = 0xfe,
>      OPC1_16_SB_JNZ                                   = 0xee,
>      OPC1_16_SBR_JNZ                                  = 0xf6,
>      OPC1_16_SBR_JNZ_A                                = 0x7c,
>      OPC1_16_SBRN_JNZ_T                               = 0xae,
>      OPC1_16_SB_JZ                                    = 0x6e,
> +    OPC1_16_SB_JNE                                   = 0xfe,

This is the same opcode as OPC1_16_SBR_JNE2. Don't duplicate it.

  reply	other threads:[~2018-02-20 15:51 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-19  6:18 [Qemu-devel] [PATCH 0/5] tricore: added small features + fixed wrong masks David Brenken
2018-02-19  6:18 ` [Qemu-devel] [PATCH 1/5] tricore: added some missing cpu instructions David Brenken
2018-02-20 15:48   ` Bastian Koppelmann [this message]
2018-02-19  6:18 ` [Qemu-devel] [PATCH 2/5] tricore: added CORE_ID David Brenken
2018-02-20 15:53   ` Bastian Koppelmann
2018-02-19  6:18 ` [Qemu-devel] [PATCH 3/5] tricore: fixed wrong masking of IE David Brenken
2018-02-20 15:59   ` Bastian Koppelmann
2018-02-19  6:18 ` [Qemu-devel] [PATCH 4/5] tricore: fixed wrong mask of PCXI_PIE David Brenken
2018-02-20 16:03   ` Bastian Koppelmann
2018-02-19  6:18 ` [Qemu-devel] [PATCH 5/5] tricore: fixed wrong shifting of PCXI PIE David Brenken
2018-02-20 15:48 ` [Qemu-devel] [PATCH 0/5] tricore: added small features + fixed wrong masks Bastian Koppelmann

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