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From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Rolnik <mrolnik@gmail.com>
Cc: Sarah Harris <S.E.Harris@kent.ac.uk>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH RFC v20 3/8] target/avr: Add mechanism to check for active debugger connection
Date: Mon, 3 Jun 2019 11:36:55 -0500	[thread overview]
Message-ID: <3bc0d426-bd59-055d-a010-b136cba555bf@linaro.org> (raw)
In-Reply-To: <CAK4993hXTOSoW5FFjeur+pLzT18c-C=vwao-904ASyqMsT5eMQ@mail.gmail.com>

On 6/3/19 11:29 AM, Michael Rolnik wrote:
> 1. There's a break
> instruction https://www.microchip.com/webdoc/avrassembler/avrassembler.wb_BREAK.html
> 2. There's a set of tests that use break. 
> 
> So I assume I have to implement this instruction as described in the spec.

The spec talks about fuses, not gdb.  A valid implementation of this
instruction is a no-op -- it say so right there in the spec.

What does it mean to "test" break?  AFAIK, you can't test this at all from
within the cpu itself, since it does not generate a cpu-level exception.

If gdb is setting a breakpoint via -S, it should be done via cpu_breakpoint_test.



> On Mon, Jun 3, 2019, 6:44 PM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
> 
>     On 6/1/19 4:12 PM, Michael Rolnik wrote:
>     > Hi Richard.
>     >
>     > If I implement it this way
>     >
>     > ```
>     >  static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
>     >  {
>     >      if (avr_feature(ctx->env, AVR_FEATURE_BREAK) == false) {
>     >          gen_helper_unsupported(cpu_env);
>     >      } else {
>     >          tcg_gen_movi_tl(cpu_pc, ctx->inst[0].npc);
>     >          gen_helper_debug(cpu_env);
>     >      }
>     >
>     >      ctx->bstate = BS_EXCP;
>     >
>     >      return true;
>     >  }
>     > ```
>     >
>     > qemu (without -s -S flags) crashes when debugger is not connected
> 
>     I was not suggesting using the internal qemu EXCP_DEBUG, but another AVR
>     specific exception, much the same way as every other cpu has a cpu-specific
>     debug exception.
> 
>     Or perhaps always do nothing.  Why is gdb insertting BREAK in the first place?
>      It should be using the "hardware breakpoint" support that qemu advertises as
>     part of the gdbstub protocol, and that you support here:
> 
>     > +        if (unlikely(cpu_breakpoint_test(cs, OFFSET_CODE + cpc * 2, BP_ANY))
>     > +                 || cpu_breakpoint_test(cs, OFFSET_DATA + cpc * 2,
>     BP_ANY)) {
>     > +            tcg_gen_movi_i32(cpu_pc, cpc);
>     > +            gen_helper_debug(cpu_env);
>     > +            ctx.bstate = BS_EXCP;
>     > +            goto done_generating;
>     > +        }



  reply	other threads:[~2019-06-03 16:39 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-30 19:07 [Qemu-devel] [PATCH RFC v20 0/8] QEMU AVR 8 bit cores Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 1/8] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-05-31  8:02   ` Igor Mammedov
2019-05-31  8:15     ` Michael Rolnik
2019-05-31  9:56       ` Igor Mammedov
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 2/8] target/avr: Add instruction helpers Michael Rolnik
2019-05-31 13:50   ` Richard Henderson
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 3/8] target/avr: Add mechanism to check for active debugger connection Michael Rolnik
2019-05-31 13:54   ` Richard Henderson
2019-06-01 21:12     ` Michael Rolnik
2019-06-03 15:44       ` Richard Henderson
2019-06-03 16:29         ` Michael Rolnik
2019-06-03 16:36           ` Richard Henderson [this message]
2019-06-03 17:04             ` Michael Rolnik
2019-06-05  7:20               ` Michael Rolnik
2019-06-05 14:36                 ` Richard Henderson
2019-06-05 15:19                   ` Michael Rolnik
2019-06-05 16:06                     ` Richard Henderson
2019-06-05 16:10                     ` Alex Bennée
2019-06-05 17:57                       ` Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 4/8] target-avr: Add instruction decoding Michael Rolnik
2019-05-31 14:45   ` Richard Henderson
2019-06-03 20:13     ` Michael Rolnik
2019-06-03 21:48       ` Richard Henderson
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation Michael Rolnik
2019-05-31 15:31   ` Richard Henderson
2019-06-02  3:44     ` Michael Rolnik
2019-06-03 15:31       ` Richard Henderson
2019-06-03 15:34         ` Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 6/8] target/avr: Add limited support for USART and 16 bit timer peripherals Michael Rolnik
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 7/8] target/avr: Add example board configuration Michael Rolnik
2019-05-31  8:06   ` Igor Mammedov
2019-05-30 19:07 ` [Qemu-devel] [PATCH RFC v20 8/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file Michael Rolnik
2019-05-31 14:50   ` Eric Blake
2019-06-01 21:20     ` Michael Rolnik
2019-06-03 19:47       ` Eric Blake
2019-06-03 19:53         ` Michael Rolnik
2019-05-30 20:16 ` [Qemu-devel] [PATCH RFC v20 0/8] QEMU AVR 8 bit cores no-reply

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