From: Stefan Berger <stefanb@linux.ibm.com>
To: Chalapathi V <chalapathi.v@linux.ibm.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com,
clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com,
saif.abrar@linux.vnet.ibm.com
Subject: Re: [PATCH v1 2/5] hw/ppc: SPI controller model - registers implementation
Date: Thu, 7 Mar 2024 14:11:47 -0500 [thread overview]
Message-ID: <3bfc8f83-f504-4039-8cc3-0c0fb6382692@linux.ibm.com> (raw)
In-Reply-To: <6ab8bb8e-5126-4322-bb91-6709e46c444a@linux.ibm.com>
On 3/7/24 13:54, Stefan Berger wrote:
>
>
> On 2/7/24 11:08, Chalapathi V wrote:
>> +#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0 , 7)
No space before the ',' ==> PPC_BITMASK(0, 7)
next prev parent reply other threads:[~2024-03-07 19:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-07 16:08 [PATCH v1 0/5] hw/ppc: SPI model Chalapathi V
2024-02-07 16:08 ` [PATCH v1 1/5] hw/ppc: SPI responder model Chalapathi V
2024-03-08 16:00 ` Stefan Berger
2024-02-07 16:08 ` [PATCH v1 2/5] hw/ppc: SPI controller model - registers implementation Chalapathi V
2024-03-07 18:54 ` Stefan Berger
2024-03-07 19:11 ` Stefan Berger [this message]
2024-03-08 15:17 ` Stefan Berger
2024-02-07 16:08 ` [PATCH v1 3/5] hw/ppc: SPI controller model - sequencer and shifter Chalapathi V
2024-03-08 19:36 ` Stefan Berger
2024-02-07 16:08 ` [PATCH v1 4/5] hw/ppc: SPI SEEPROM model Chalapathi V
2024-03-08 15:14 ` Stefan Berger
2024-02-07 16:08 ` [PATCH v1 5/5] hw/ppc: SPI controller wiring to P10 chip and create seeprom device Chalapathi V
2024-03-01 16:17 ` [PATCH v1 0/5] hw/ppc: SPI model Chalapathi V
2024-03-01 16:36 ` Cédric Le Goater
2024-03-01 18:33 ` Chalapathi V
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