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([2602:ae:154a:9f01:acd:bde4:fbf6:cc41]) by smtp.gmail.com with ESMTPSA id bv7-20020a17090af18700b00230cbb4b6e8sm9230956pjb.24.2023.03.08.08.47.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Mar 2023 08:47:14 -0800 (PST) Message-ID: <3c2362c4-1d2f-f749-db1e-201d985e67be@linaro.org> Date: Wed, 8 Mar 2023 08:47:12 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2 8/9] async: update documentation of the memory barriers Content-Language: en-US To: Paolo Bonzini , qemu-devel@nongnu.org Cc: gshan@redhat.com, eesposit@redhat.com, david@redhat.com, stefanha@redhat.com, cohuck@redhat.com, eauger@redhat.com References: <20230306223306.84383-1-pbonzini@redhat.com> <20230306223306.84383-9-pbonzini@redhat.com> <10e49543-b4f8-f22c-a9ab-e6340c6a0074@linaro.org> <12ea9d46-1e95-62a1-70f7-d77a66b44bd0@redhat.com> <9da5c9c5-0675-157d-f099-2b0b14c26002@redhat.com> From: Richard Henderson In-Reply-To: <9da5c9c5-0675-157d-f099-2b0b14c26002@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/8/23 02:49, Paolo Bonzini wrote: > On 3/7/23 18:26, Richard Henderson wrote: >> On 3/7/23 09:00, Paolo Bonzini wrote: >>> while QSLIST_REMOVE_HEAD in the dequeuing thread is not ordered at all: >>> >>>          y.store(0, mo_relaxed);           // QSLIST_REMOVE_HEAD >>>          x.store(0, mo_release);           // fetch_and >>> >>>> As I read aio_bh_queue, this is exactly the situation you describe in patch 1 >>>> justifying the introduction of the new barriers. >>> >>> Only store-store reordering is required between QSLIST_REMOVE_HEAD and >>> atomic_fetch_and(); and that one *is* blocked by atomic_fetch_and(), since mo_seq_cst >>> is a superset of both mo_release.  The new barriers are needed for store-load reordering. >> >> In patch 1 you say: >> >> # in C11, sequentially consistent atomics (except for seq-cst fences) >> # only affect the ordering of sequentially consistent operations. >> >> and the store in QSLIST_REMOVE_HEAD is not a sequentially consistent operation. >> Therefore by your own logic we must have a separate barrier here. > > You're right that the comment is contradictory. > > It's the comment that is wrong.  The right text should be > > --- > in C11, with the exception of seq-cst fences, the order established by sequentially > consistent atomics does not propagate to other memory accesses on either side of the > seq-cst atomic.  As far as those are concerned, loads performed by a seq-cst atomic are > just acquire loads, and stores are just release stores.  Even though loads that occur > after a RMW operation cannot move above the load, they can still sneak above the store! > --- Ok, thanks. >> I wonder if your definition/description of smp_mb__before_rmw() isn't actively >> misleading in this case. >> >> - We could drop it entirely and be less confusing, by not having to explain it. >> - We could define it as  signal_barrier() for all hosts, simply to fix the >>    compiler-theoretic reordering problem. > > The case that I was imagining for smp_mb__before_rmw() is something like this: > >     wake_me = true; >     smp_mb__before_rmw(); >     if (qatomic_xchg(&can_sleep, true)) { ... } > > where you really need a full barrier. What is different about this that doesn't apply to the remove-head case we've been talking about? r~