From: Bibo Mao <maobibo@loongson.cn>
To: Song Gao <gaosong@loongson.cn>
Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com
Subject: Re: [PATCH v5 07/11] hw/loongarch: Implement avec controller imput and output pins
Date: Mon, 14 Jul 2025 17:38:46 +0800 [thread overview]
Message-ID: <3c7fc540-d6d9-ddcd-fde0-db614b97c6a7@loongson.cn> (raw)
In-Reply-To: <20250711085915.3042395-8-gaosong@loongson.cn>
On 2025/7/11 下午4:59, Song Gao wrote:
> the AVEC controller supports 256*256 irqs input, all the irqs connect CPU INT_AVEC irq
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/intc/loongarch_avec.c | 20 ++++++++++++++++++++
> hw/loongarch/virt.c | 11 +++++++++--
> target/loongarch/cpu.h | 3 ++-
> 3 files changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
> index 253bab5461..1f9f376898 100644
> --- a/hw/intc/loongarch_avec.c
> +++ b/hw/intc/loongarch_avec.c
> @@ -38,7 +38,12 @@ static const MemoryRegionOps loongarch_avec_ops = {
>
> static void loongarch_avec_realize(DeviceState *dev, Error **errp)
> {
> + LoongArchAVECState *s = LOONGARCH_AVEC(dev);
> LoongArchAVECClass *lac = LOONGARCH_AVEC_GET_CLASS(dev);
> + MachineState *machine = MACHINE(qdev_get_machine());
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> + const CPUArchIdList *id_list;
> + int i;
>
> Error *local_err = NULL;
> lac->parent_realize(dev, &local_err);
> @@ -47,6 +52,21 @@ static void loongarch_avec_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + assert(mc->possible_cpu_arch_ids);
> + id_list = mc->possible_cpu_arch_ids(machine);
> + s->num_cpu = id_list->len;
> + s->cpu = g_new(AVECCore, s->num_cpu);
> + if (s->cpu == NULL) {
> + error_setg(errp, "Memory allocation for AVECCore fail");
> + return;
> + }
> +
> + for (i = 0; i < s->num_cpu; i++) {
> + s->cpu[i].arch_id = id_list->cpus[i].arch_id;
> + s->cpu[i].cpu = CPU(id_list->cpus[i].cpu);
> + qdev_init_gpio_out(dev, &s->cpu[i].parent_irq, 1);
> + }
> +
> return;
> }
>
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index b420d1def9..e3ab165cc5 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -380,7 +380,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState *lvms)
> }
> }
>
> -static void virt_irq_init(LoongArchVirtMachineState *lvms)
> +static void virt_irq_init(LoongArchVirtMachineState *lvms, MachineState *ms)
The extra parameter machine is not necessary, it can be acquired from
the first parameter lvms, such as:
MachineState *ms = MACHINE(lvms);
> {
> DeviceState *pch_pic, *pch_msi;
> DeviceState *ipi, *extioi, *avec;
> @@ -470,6 +470,13 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
> sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal);
> memory_region_add_subregion(get_system_memory(), VIRT_AVEC_BASE,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0));
> + CPUState *cpu_state;
> + DeviceState *cpudev;
It is strange to declare new variable between sentences, I think it
should be put in the beginning of function.
Regards
Bibo Mao
> + for (int cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + cpu_state = qemu_get_cpu(cpu);
> + cpudev = DEVICE(cpu_state);
> + qdev_connect_gpio_out(avec, cpu, qdev_get_gpio_in(cpudev, INT_AVEC));
> + }
> }
>
> /* Create EXTIOI device */
> @@ -838,7 +845,7 @@ static void virt_init(MachineState *machine)
> }
>
> /* Initialize the IO interrupt subsystem */
> - virt_irq_init(lvms);
> + virt_irq_init(lvms, machine);
> lvms->machine_done.notify = virt_done;
> qemu_add_machine_init_done_notifier(&lvms->machine_done);
> /* connect powerdown request */
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 208d3e0cd3..556e9dabb9 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -217,9 +217,10 @@ FIELD(CSR_CRMD, WE, 9, 1)
> extern const char * const regnames[32];
> extern const char * const fregnames[32];
>
> -#define N_IRQS 13
> +#define N_IRQS 15
> #define IRQ_TIMER 11
> #define IRQ_IPI 12
> +#define INT_AVEC 14
>
> #define LOONGARCH_STLB 2048 /* 2048 STLB */
> #define LOONGARCH_MTLB 64 /* 64 MTLB */
>
next prev parent reply other threads:[~2025-07-14 9:44 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-11 8:59 [PATCH v5 00/11] hw/loongarch: add the advanced extended interrupt controllers (AVECINTC) support Song Gao
2025-07-11 8:59 ` [PATCH v5 01/11] target/loongarch: move some machine define to virt.h Song Gao
2025-07-11 8:59 ` [PATCH v5 02/11] hw/loongarch: add virt feature avecintc support Song Gao
2025-07-15 1:02 ` Bibo Mao
2025-07-15 1:32 ` gaosong
2025-07-11 8:59 ` [PATCH v5 03/11] hw/loongarch: add misc register supoort avecintc Song Gao
2025-07-11 8:59 ` [PATCH v5 04/11] loongarch: add a advance interrupt controller device Song Gao
2025-07-11 8:59 ` [PATCH v5 05/11] target/loongarch: add msg interrupt CSR registers Song Gao
2025-07-14 9:35 ` Bibo Mao
2025-07-11 8:59 ` [PATCH v5 06/11] hw/loongarch: AVEC controller add a MemoryRegion Song Gao
2025-07-11 8:59 ` [PATCH v5 07/11] hw/loongarch: Implement avec controller imput and output pins Song Gao
2025-07-14 9:38 ` Bibo Mao [this message]
2025-07-11 8:59 ` [PATCH v5 08/11] hw/loongarch: Implement avec set irq Song Gao
2025-07-14 9:29 ` Bibo Mao
2025-07-17 8:33 ` gaosong
2025-08-28 8:34 ` Bibo Mao
2025-07-11 8:59 ` [PATCH v5 09/11] target/loongarch: CPU enable msg interrupts Song Gao
2025-07-14 9:46 ` Bibo Mao
2025-07-11 8:59 ` [PATCH v5 10/11] target/loongarch:Implement csrrd CSR_MSGIR register Song Gao
2025-07-11 8:59 ` [PATCH v5 11/11] hw/loongarch: Implement AVEC plug/unplug interfaces Song Gao
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