From: Paolo Bonzini <pbonzini@redhat.com>
To: "Radim Krčmář" <rkrcmar@redhat.com>,
qemu-devel@nongnu.org, "Richard Henderson" <rth@twiddle.net>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
kvm@vger.kernel.org, "Boris Petkov" <bp@suse.de>,
"Tony Luck" <tony.luck@intel.com>,
"Andi Kleen" <andi.kleen@intel.com>,
"Ashok Raj" <ashok.raj@intel.com>
Subject: Re: [Qemu-devel] [PATCH v3 1/2] target-i386: KVM: add basic Intel LMCE support
Date: Mon, 13 Jun 2016 10:33:12 +0200 [thread overview]
Message-ID: <3c94eb13-8d83-a66d-5ee7-0e63a4cc4501@redhat.com> (raw)
In-Reply-To: <20160613075550.4ikqkejen27zlcpr@hz-desktop>
On 13/06/2016 09:55, Haozhong Zhang wrote:
> Currently, only VMX bits (bit 1 & 2), LMCE bit (bit 20) as well as
> lock bit (bit 0) in MSR_IA32_FEATURE_CONTROL are used for guest. The
> availability of features indicated by those bits (except the lock bit)
> can be discovered from cpuid and other MSR, so it looks not necessary
> to publish them via fw_cfg. Or do you have other concerns?
I would prefer to avoid having to change the firmware (SeaBIOS and OVMF)
every time a new bit is added. Using fw_cfg makes it possible to
develop the feature in the firmware once and for all.
Paolo
next prev parent reply other threads:[~2016-06-13 8:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-03 6:09 [Qemu-devel] [PATCH v3 0/2] Add QEMU support for Intel local MCE Haozhong Zhang
2016-06-03 6:09 ` [Qemu-devel] [PATCH v3 1/2] target-i386: KVM: add basic Intel LMCE support Haozhong Zhang
2016-06-03 15:57 ` Radim Krčmář
2016-06-05 15:32 ` Haozhong Zhang
2016-06-08 11:32 ` Paolo Bonzini
2016-06-13 7:55 ` Haozhong Zhang
2016-06-13 8:33 ` Paolo Bonzini [this message]
2016-06-13 10:01 ` Haozhong Zhang
2016-06-13 10:07 ` Paolo Bonzini
2016-06-13 10:09 ` Haozhong Zhang
2016-06-04 10:15 ` Boris Petkov
2016-06-05 15:35 ` Haozhong Zhang
2016-06-04 10:34 ` Boris Petkov
2016-06-04 21:03 ` Eduardo Habkost
2016-06-07 9:41 ` Haozhong Zhang
2016-06-07 11:47 ` Haozhong Zhang
2016-06-05 15:41 ` Haozhong Zhang
2016-06-08 11:34 ` Paolo Bonzini
2016-06-09 6:52 ` Haozhong Zhang
2016-06-07 20:10 ` Eduardo Habkost
2016-06-08 1:43 ` Haozhong Zhang
2016-06-03 6:09 ` [Qemu-devel] [PATCH v3 2/2] target-i386: add migration support for Intel LMCE Haozhong Zhang
2016-06-07 20:18 ` Eduardo Habkost
2016-06-08 1:56 ` Haozhong Zhang
2016-06-08 11:36 ` Paolo Bonzini
2016-06-09 7:16 ` Haozhong Zhang
2016-06-09 8:23 ` Paolo Bonzini
2016-06-03 6:38 ` [Qemu-devel] [PATCH v3 0/2] Add QEMU support for Intel local MCE Haozhong Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3c94eb13-8d83-a66d-5ee7-0e63a4cc4501@redhat.com \
--to=pbonzini@redhat.com \
--cc=andi.kleen@intel.com \
--cc=ashok.raj@intel.com \
--cc=bp@suse.de \
--cc=ehabkost@redhat.com \
--cc=kvm@vger.kernel.org \
--cc=mst@redhat.com \
--cc=mtosatti@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rkrcmar@redhat.com \
--cc=rth@twiddle.net \
--cc=tony.luck@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).