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References: <20160603060944.17373-1-haozhong.zhang@intel.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <3c94eb13-8d83-a66d-5ee7-0e63a4cc4501@redhat.com>
Date: Mon, 13 Jun 2016 10:33:12 +0200
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Subject: Re: [Qemu-devel] [PATCH v3 1/2] target-i386: KVM: add basic Intel
 LMCE support
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To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>, qemu-devel@nongnu.org, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, kvm@vger.kernel.org, Boris Petkov <bp@suse.de>, Tony Luck <tony.luck@intel.com>, Andi Kleen <andi.kleen@intel.com>, Ashok Raj <ashok.raj@intel.com>



On 13/06/2016 09:55, Haozhong Zhang wrote:
> Currently, only VMX bits (bit 1 & 2), LMCE bit (bit 20) as well as
> lock bit (bit 0) in MSR_IA32_FEATURE_CONTROL are used for guest. The
> availability of features indicated by those bits (except the lock bit)
> can be discovered from cpuid and other MSR, so it looks not necessary
> to publish them via fw_cfg. Or do you have other concerns?

I would prefer to avoid having to change the firmware (SeaBIOS and OVMF)
every time a new bit is added.  Using fw_cfg makes it possible to
develop the feature in the firmware once and for all.

Paolo