From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Ziqiao Kong <ziqiaokong@gmail.com>, qemu-devel@nongnu.org
Cc: qemu-trivial@nongnu.org, alistair.francis@wdc.com,
richard.henderson@linaro.org
Subject: Re: [PATCH v2 1/1] target/riscv: fix endless translation loop on big endian systems
Date: Mon, 14 Apr 2025 12:41:43 +0200 [thread overview]
Message-ID: <3c9e1adc-eb4e-49f4-be32-b273a5a161b8@linaro.org> (raw)
In-Reply-To: <20250414034626.3491489-2-ziqiaokong@gmail.com>
Hi,
On 14/4/25 05:46, Ziqiao Kong wrote:
> On big endian systems, pte and updated_pte hold big endian host data
> while pte_pa points to little endian target data. This means the branch
> at cpu_helper.c:1669 will be always satisfied and restart translation,
> causing an endless translation loop.
>
Cc: qemu-stable@nongnu.org
Fixes: 0c3e702aca7 ("RISC-V CPU Helpers")
> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
> ---
> target/riscv/cpu_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 6c4391d96b..bc146771c8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1662,9 +1662,9 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1);
> target_ulong old_pte;
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> - old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
> + old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pte), cpu_to_le32(updated_pte));
> } else {
> - old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
> + old_pte = qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_to_le64(updated_pte));
> }
> if (old_pte != pte) {
> goto restart;
If PTEs are always stored in LE order, maybe what we want is earlier:
-- >8 --
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 619c76cc001..b6ac2800240 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1464,5 +1464,5 @@ static int get_physical_address(CPURISCVState
*env, hwaddr *physical,
if (riscv_cpu_mxl(env) == MXL_RV32) {
- pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
+ pte = address_space_ldl_le(cs->as, pte_addr, attrs, &res);
} else {
- pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
+ pte = address_space_ldq_le(cs->as, pte_addr, attrs, &res);
}
---
next prev parent reply other threads:[~2025-04-14 10:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-14 3:46 [PATCH v2 0/1] Fix endless translation loop of riscv Ziqiao Kong
2025-04-14 3:46 ` [PATCH v2 1/1] target/riscv: fix endless translation loop on big endian systems Ziqiao Kong
2025-04-14 10:41 ` Philippe Mathieu-Daudé [this message]
2025-04-14 11:17 ` Ziqiao Kong
2025-04-14 16:59 ` Ziqiao Kong
2025-04-14 17:38 ` Philippe Mathieu-Daudé
[not found] ` <CAM0BWNBNrjJ6UuF+TRtkuEesLatnY1pzSjyaiPVDeKSMF8no-A@mail.gmail.com>
2025-04-15 7:04 ` Ziqiao Kong
2025-04-15 7:15 ` Philippe Mathieu-Daudé
2025-04-15 7:19 ` Ziqiao Kong
2025-04-15 7:22 ` Ziqiao Kong
2025-04-15 7:40 ` Ziqiao Kong
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