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From: "Cédric Le Goater" <clg@kaod.org>
To: Kane Chen <kane_chen@aspeedtech.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Steven Lee <steven_lee@aspeedtech.com>,
	Troy Lee <leetroy@gmail.com>,
	Jamin Lin <jamin_lin@aspeedtech.com>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Joel Stanley <joel@jms.id.au>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com
Subject: Re: [SPAM] [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
Date: Tue, 2 Sep 2025 07:32:44 +0200	[thread overview]
Message-ID: <3ca1ebf4-ad70-4738-b96c-41f5d8abfe31@kaod.org> (raw)
In-Reply-To: <20250812094011.2617526-8-kane_chen@aspeedtech.com>

On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> 
> The OTP space contains three types of entries: data, conf, and strap.
> Data entries consist of two DWORDs, while the other types contain
> only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to
> store the second DWORD when reading from the OTP data region.
> 
> With this enhancement, OTP reads now correctly return both DWORDs for
> data entries via the CAMP registers, along with improved address
> validation and error handling.
> 
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/misc/aspeed_sbc.c | 27 +++++++++++++++++++++++++++
>   1 file changed, 27 insertions(+)
> 
> diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
> index 052c70fd42..787e2d0489 100644
> --- a/hw/misc/aspeed_sbc.c
> +++ b/hw/misc/aspeed_sbc.c
> @@ -22,6 +22,7 @@
>   #define R_ADDR          (0x010 / 4)
>   #define R_STATUS        (0x014 / 4)
>   #define R_CAMP1         (0x020 / 4)
> +#define R_CAMP2         (0x024 / 4)
>   #define R_QSR           (0x040 / 4)
>   
>   /* R_STATUS */
> @@ -50,6 +51,8 @@
>   #define SBC_OTP_CMD_READ 0x23b1e361
>   #define SBC_OTP_CMD_PROG 0x23b1e364
>   
> +#define OTP_DATA_DWORD_COUNT        (0x800)
> +#define OTP_TOTAL_DWORD_COUNT       (0x1000)
>   static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
>   {
>       AspeedSBCState *s = ASPEED_SBC(opaque);
> @@ -72,6 +75,16 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
>       MemTxResult ret;
>       AspeedOTPState *otp = &s->otp;
>       uint32_t value, otp_offset;
> +    bool is_data = false;
> +
> +    if (otp_addr < OTP_DATA_DWORD_COUNT) {
> +        is_data = true;
> +    } else if (otp_addr >= OTP_TOTAL_DWORD_COUNT) {
> +        qemu_log_mask(LOG_GUEST_ERROR,
> +                      "Invalid OTP addr 0x%x\n",
> +                      otp_addr);
> +        return false;
> +    }
>   
>       otp_offset = otp_addr << 2;
>       ret = address_space_read(&otp->as, otp_offset, MEMTXATTRS_UNSPECIFIED,
> @@ -85,6 +98,20 @@ static bool aspeed_sbc_otp_read(AspeedSBCState *s,
>       s->regs[R_CAMP1] = value;
>       trace_aspeed_sbc_otp_read(otp_addr, value);
>   
> +    if (is_data) {
> +        ret = address_space_read(&otp->as, otp_offset + 4,
> +                                 MEMTXATTRS_UNSPECIFIED,
> +                                 &value, sizeof(value));
> +        if (ret != MEMTX_OK) {
> +            qemu_log_mask(LOG_GUEST_ERROR,
> +                          "Failed to read OTP memory, addr = %x\n",
> +                          otp_addr);
> +            return false;
> +        }
> +        s->regs[R_CAMP2] = value;
> +        trace_aspeed_sbc_otp_read(otp_addr + 1, value);
> +    }
> +
>       return true;
>   }
>   



  reply	other threads:[~2025-09-02  5:33 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-12  9:39 [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Kane Chen via
2025-08-12  9:39 ` [PATCH v5 01/10] hw/nvram/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
2025-08-12  9:39 ` [PATCH v5 02/10] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
2025-08-12  9:40 ` [PATCH v5 03/10] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Kane Chen via
2025-08-12  9:40 ` [PATCH v5 04/10] hw/nvram/aspeed_otp: Add 'drive' property to support block backend Kane Chen via
2025-08-12  9:40 ` [PATCH v5 05/10] hw/nvram/aspeed_otp: Add OTP programming semantics and tracing Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 07/10] hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads Kane Chen via
2025-09-02  5:32   ` Cédric Le Goater [this message]
2025-08-12  9:40 ` [PATCH v5 08/10] hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers Kane Chen via
2025-09-02  5:32   ` [SPAM] " Cédric Le Goater
2025-08-12  9:40 ` [PATCH v5 09/10] tests/function/aspeed: Add OTP functional test Kane Chen via
2025-09-02  5:41   ` [SPAM] " Cédric Le Goater
2025-09-02  5:48     ` Kane Chen
2025-08-12  9:40 ` [PATCH v5 10/10] docs/system/arm/aspeed: Document OTP memory options Kane Chen via
2025-09-02  5:41   ` [SPAM] " Cédric Le Goater
2025-09-02  5:44 ` [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, tests, and docs Cédric Le Goater
2025-09-02  6:05   ` Kane Chen

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