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From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
	Alexey Baturo <baturo.alexey@gmail.com>
Cc: zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com,
	Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
	kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
Date: Fri, 19 Jan 2024 07:50:03 +1100	[thread overview]
Message-ID: <3cb918ca-27cd-4f1e-8738-306dc5280f42@linaro.org> (raw)
In-Reply-To: <CAKC1njSLR614zQk0_DAgYN1jjdg=0eUa7N1AEwwXZVNN6BwjmA@mail.gmail.com>

On 1/19/24 04:21, Deepak Gupta wrote:
> On Tue, Jan 9, 2024 at 2:31 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>>
>> From: Alexey Baturo <baturo.alexey@gmail.com>
>>
>> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>> ---
> 
>> +
>> +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
>> +{
>> +    bool virt_mem_en = false;
>> +#ifndef CONFIG_USER_ONLY
>> +    int satp_mode = 0;
>> +    int priv_mode = cpu_address_mode(env);
>> +    /* Get current PMM field */
>> +    if (riscv_cpu_mxl(env) == MXL_RV32) {
>> +        satp_mode = get_field(env->satp, SATP32_MODE);
>> +    } else {
>> +        satp_mode = get_field(env->satp, SATP64_MODE);
>> +    }
>> +    virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
>> +#endif
>> +    return virt_mem_en;
> 
> Obsessing a little bit on how to test PM enabled binaries with qemu-user.
> If we return false above then we're not allowed to test binaries with
> pointer masking enabled with qemu-user.
> That use case is not required?

In a previous round I suggested that the ifdefs are not necessary.
But for now it will always be off for qemu-user.

At some point pointer masking will be in hardware, and the kernel will gain support for 
it, and there will likely be a prctl() added for it.  At the point the kernel finalizes 
the API, you will be able to enable pointer masking for qemu-user.


r~


  reply	other threads:[~2024-01-18 20:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-22  6:53   ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2024-01-22  7:04   ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2024-01-18 17:21   ` Deepak Gupta
2024-01-18 20:50     ` Richard Henderson [this message]
2024-01-18 22:40       ` Deepak Gupta
2024-01-20  7:37         ` Richard Henderson
2024-01-21  7:13           ` Alexey Baturo
2024-01-23 17:44             ` Deepak Gupta
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2024-01-22  7:01   ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-22  7:01   ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-22  6:54   ` Alistair Francis
2024-01-22  6:52 ` [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alistair Francis

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