From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
Date: Fri, 19 Feb 2021 08:11:53 -0800 [thread overview]
Message-ID: <3cd7260d-4c09-696c-6a8d-0a74920adcdd@linaro.org> (raw)
In-Reply-To: <20210219095902.3602-1-frank.chang@sifive.com>
On 2/19/21 1:59 AM, frank.chang@sifive.com wrote:
> +/* Skip mem_idx bits */
> +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
Why not just add the mem_idx field to the list?
The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and will
be a continuing source of errors.
r~
next prev parent reply other threads:[~2021-02-19 16:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-19 9:59 [PATCH] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-02-19 16:11 ` Richard Henderson [this message]
2021-02-20 5:14 ` Frank Chang
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