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Wed, 29 Oct 2025 06:14:00 -0700 (PDT) Received: from [10.240.88.227] ([172.56.16.75]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5aea78e2fd4sm5585459173.26.2025.10.29.06.13.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Oct 2025 06:14:00 -0700 (PDT) Message-ID: <3cdafcc5-dc91-4612-b53b-8b6ad92de7b2@linaro.org> Date: Wed, 29 Oct 2025 14:13:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 24/37] target/arm: Use flush_if_asid_change in vmsa_ttbr_write To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20251014200718.422022-1-richard.henderson@linaro.org> <20251014200718.422022-25-richard.henderson@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/20/25 16:08, Peter Maydell wrote: > On Tue, 14 Oct 2025 at 21:17, Richard Henderson > wrote: >> >> Only flush the subset of tlbs that are affected by the ttbr >> register to which we are writing. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/helper.c | 19 ++++++++++++++----- >> 1 file changed, 14 insertions(+), 5 deletions(-) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index c6d290ce7c..2b55e219c2 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -2943,11 +2943,20 @@ static void flush_if_asid_change(CPUARMState *env, const ARMCPRegInfo *ri, >> static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> - /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ >> - if (cpreg_field_type(ri) == MO_64 && >> - extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { >> - ARMCPU *cpu = env_archcpu(env); >> - tlb_flush(CPU(cpu)); >> + /* >> + * If the ASID changes (with a 64-bit write), we must flush the TLB. >> + * The non-secure ttbr registers affect the EL1 regime; >> + * the secure ttbr registers affect the AA32 EL3 regime. >> + */ >> + if (cpreg_field_type(ri) == MO_64) { >> + flush_if_asid_change(env, ri, value, >> + ri->secure & ARM_CP_SECSTATE_S >> + ? (ARMMMUIdxBit_E30_0 | >> + ARMMMUIdxBit_E30_3_PAN | >> + ARMMMUIdxBit_E3) >> + : (ARMMMUIdxBit_E10_1 | >> + ARMMMUIdxBit_E10_1_PAN | >> + ARMMMUIdxBit_E10_0)); >> } > > What's the value of ri->secure here for the case where EL3 is > AArch64 and we're in Secure EL1 at AArch32 ? Um.. the state of the cpu doesn't apply. ri->secure is true only for TTBR[01]_S. I'm not sure what the question is? r~