Re: [PATCH v2 4/8] intc/grlib_irqmp: implements multicore irq

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 16/1/24 14:02, Clément Chigot wrote:
> Now there is an ncpus property, use it in order to deliver the IRQ to
> multiple CPU.
> 
> Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
> Signed-off-by: Clément Chigot <chigot@adacore.com>
> ---
>   hw/intc/grlib_irqmp.c         | 43 ++++++++++++++++++-----------------
>   hw/sparc/leon3.c              |  3 ++-
>   include/hw/intc/grlib_irqmp.h |  2 +-
>   3 files changed, 25 insertions(+), 23 deletions(-)


>   static void grlib_irqmp_check_irqs(IRQMPState *state)
>   {
> -    uint32_t      pend   = 0;
> -    uint32_t      level0 = 0;
> -    uint32_t      level1 = 0;
> +    uint32_t pend = 0;
> +    uint32_t level0 = 0;
> +    uint32_t level1 = 0;
> +    int i;
>   
>       assert(state != NULL);
>       assert(state->parent != NULL);
>   
> -    /* IRQ for CPU 0 (no SMP support) */
> -    pend = (state->pending | state->force[0])
> -        & state->mask[0];
> -
> -    level0 = pend & ~state->level;
> -    level1 = pend &  state->level;
> +    for (i = 0; i < state->parent->ncpus; i++) {
> +        pend = (state->pending | state->force[i]) & state->mask[i];
> +        level0 = pend & ~state->level;
> +        level1 = pend &  state->level;

     for (unsigned i = 0; i < state->parent->ncpus; i++) {
         uint32_t pend = (state->pending | state->force[i])
                         & state->mask[i];
         uint32_t level0 = pend & ~state->level;
         uint32_t level1 = pend &  state->level;

>   
> -    trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
> -                                 state->mask[0], level1, level0);
> +        trace_grlib_irqmp_check_irqs(state->pending, state->force[i],
> +                                     state->mask[i], level1, level0);
>   
> -    /* Trigger level1 interrupt first and level0 if there is no level1 */
> -    qemu_set_irq(state->parent->irq, level1 ?: level0);
> +        /* Trigger level1 interrupt first and level0 if there is no level1 */
> +        qemu_set_irq(state->parent->irq[i], level1 ?: level0);
> +    }
>   }
>   
> -static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
> +static void grlib_irqmp_ack_mask(IRQMPState *state, int cpu, uint32_t mask)

unsigned cpu, ...

>   {
>       /* Clear registers */
>       state->pending  &= ~mask;
> -    state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
> +    state->force[cpu] &= ~mask;
>   
>       grlib_irqmp_check_irqs(state);
>   }
>   
> -void grlib_irqmp_ack(DeviceState *dev, int intno)
> +void grlib_irqmp_ack(DeviceState *dev, int cpu, int intno)

unsigned cpu, ...

>   {
>       IRQMP        *irqmp = GRLIB_IRQMP(dev);
>       IRQMPState   *state;
> @@ -133,7 +133,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno)
>   
>       trace_grlib_irqmp_ack(intno);
>   
> -    grlib_irqmp_ack_mask(state, mask);
> +    grlib_irqmp_ack_mask(state, cpu, mask);
>   }
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>