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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-456297f8621sm3172435e9.4.2025.07.14.23.57.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 23:57:28 -0700 (PDT) Message-ID: <3cfa886a-c0f2-40ae-af16-d9f019ab70d3@linaro.org> Date: Tue, 15 Jul 2025 08:57:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE To: qemu-devel@nongnu.org, Jiaxun Yang , Aleksandar Rikalo , Hansni Bu <1926277@bugs.launchpad.net> Cc: Aleksandar Rikalo , "Edgar E . Iglesias" , Aurelien Jarno References: <20210427133343.159718-1-f4bug@amsat.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20210427133343.159718-1-f4bug@amsat.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Ping? On 27/4/21 15:33, Philippe Mathieu-Daudé wrote: > According to the 'MIPS MT Application-Specific Extension' manual: > > If the VPE executing the instruction is not a Master VPE, > with the MVP bit of the VPEConf0 register set, the EVP bit > is unchanged by the instruction. > > Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit > if executed on a master VPE. > > Reported-by: Hansni Bu > Buglink: https://bugs.launchpad.net/qemu/+bug/1926277 > Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs") > Signed-off-by: Philippe Mathieu-Daudé > --- > Supersedes: <20210427103555.112652-1-f4bug@amsat.org> > v2: Check VPEConf0.MVP bit (hansni) > --- > target/mips/cp0_helper.c | 32 ++++++++++++++++++-------------- > 1 file changed, 18 insertions(+), 14 deletions(-) > > diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c > index aae2af6eccc..d5f274f5cdf 100644 > --- a/target/mips/cp0_helper.c > +++ b/target/mips/cp0_helper.c > @@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env) > CPUState *other_cs = first_cpu; > target_ulong prev = env->mvp->CP0_MVPControl; > > - CPU_FOREACH(other_cs) { > - MIPSCPU *other_cpu = MIPS_CPU(other_cs); > - /* Turn off all VPEs except the one executing the dvpe. */ > - if (&other_cpu->env != env) { > - other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); > - mips_vpe_sleep(other_cpu); > + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { > + CPU_FOREACH(other_cs) { > + MIPSCPU *other_cpu = MIPS_CPU(other_cs); > + /* Turn off all VPEs except the one executing the dvpe. */ > + if (&other_cpu->env != env) { > + other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); > + mips_vpe_sleep(other_cpu); > + } > } > } > return prev; > @@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env) > CPUState *other_cs = first_cpu; > target_ulong prev = env->mvp->CP0_MVPControl; > > - CPU_FOREACH(other_cs) { > - MIPSCPU *other_cpu = MIPS_CPU(other_cs); > + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { > + CPU_FOREACH(other_cs) { > + MIPSCPU *other_cpu = MIPS_CPU(other_cs); > > - if (&other_cpu->env != env > - /* If the VPE is WFI, don't disturb its sleep. */ > - && !mips_vpe_is_wfi(other_cpu)) { > - /* Enable the VPE. */ > - other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); > - mips_vpe_wake(other_cpu); /* And wake it up. */ > + if (&other_cpu->env != env > + /* If the VPE is WFI, don't disturb its sleep. */ > + && !mips_vpe_is_wfi(other_cpu)) { > + /* Enable the VPE. */ > + other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); > + mips_vpe_wake(other_cpu); /* And wake it up. */ > + } > } > } > return prev;