Re: [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes

["Janeczek, Craig" <jancraig@amazon.com>]

It is possible but due to the non-uniform nature of the bit fields which indicate the instructions the mask used might end up being instruction specific. This would lead to a tiered approach where the current enum would be the top level, then each group under there might have its own enum, mask and switch statement.

-----Original Message-----
From: Aleksandar Markovic <amarkovic@wavecomp.com> 
Sent: Friday, August 31, 2018 2:59 PM
To: Janeczek, Craig <jancraig@amazon.com>; qemu-devel@nongnu.org
Cc: aurelien@aurel32.net; Petar Jovanovic <pjovanovic@wavecomp.com>; Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH v4 2/9] target/mips: Add all MXU opcodes

> 
> ________________________________________
> From: Craig Janeczek <jancraig@amazon.com>
> Sent: Thursday, August 30, 2018 9:30 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; aurelien@aurel32.net; Craig Janeczek
> Subject: [PATCH v4 2/9] target/mips: Add all MXU opcodes
> 
> Adds all MXU opcodes to the opcode enum.
> 
> Signed-off-by: Craig Janeczek <jancraig@amazon.com>
> ---
>  v1
>     - NA
>  v2
>     - NA
>  v3
>     - Initial patch, split out from prior first patch
>  v4
>     - separate MXU opcodes into their own enum
> 
>  target/mips/translate.c | 60 
> +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 




> diff --git a/target/mips/translate.c b/target/mips/translate.c index 
> 19b90c8735..a598f45558 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c

Hi, Craig,

There are 56 opcodes defined here. However, there are 114 MXU instructions in the MXU doc. Some other bits are used for coding missing instructions. Even in your patches, it seems, you handle some instructions that are not listed here. Is there any way to have here the complete list of opcodes, even if this involves some more complex extraction operations?

Thanks,
Aleksandar


> @@ -368,6 +368,66 @@ enum {
>      OPC_SDBBP    = 0x3F | OPC_SPECIAL2,
>  };
> +enum {
> +    /* MXU */
> +    OPC_MXU_S32MADD  = 0x00 | OPC_SPECIAL2,
> +    OPC_MXU_S32MADDU = 0x01 | OPC_SPECIAL2,
> +    OPC_MXU_D16MAX   = 0x03 | OPC_SPECIAL2,
> +    OPC_MXU_S32MSUB  = 0x04 | OPC_SPECIAL2,
> +    OPC_MXU_S32MSUBU = 0x05 | OPC_SPECIAL2,
> +    OPC_MXU_D16AVG   = 0x06 | OPC_SPECIAL2,
> +    OPC_MXU_D16CPS   = 0x07 | OPC_SPECIAL2,
> +    OPC_MXU_D16MUL   = 0x08 | OPC_SPECIAL2,
> +    OPC_MXU_D16MULF  = 0x09 | OPC_SPECIAL2,
> +    OPC_MXU_D16MAC   = 0x0A | OPC_SPECIAL2,
> +    OPC_MXU_D16MACF  = 0x0B | OPC_SPECIAL2,
> +    OPC_MXU_D16MADL  = 0x0C | OPC_SPECIAL2,
> +    OPC_MXU_S16MAD   = 0x0D | OPC_SPECIAL2,
> +    OPC_MXU_Q16ADD   = 0x0E | OPC_SPECIAL2,
> +    OPC_MXU_D16MACE  = 0x0F | OPC_SPECIAL2,
> +    OPC_MXU_S32LDD   = 0x10 | OPC_SPECIAL2,
> +    OPC_MXU_S32STD   = 0x11 | OPC_SPECIAL2,
> +    OPC_MXU_S32LDDV  = 0x12 | OPC_SPECIAL2,
> +    OPC_MXU_S32STDV  = 0x13 | OPC_SPECIAL2,
> +    OPC_MXU_S32LDI   = 0x14 | OPC_SPECIAL2,
> +    OPC_MXU_S32SDI   = 0x15 | OPC_SPECIAL2,
> +    OPC_MXU_S32LDIV  = 0x16 | OPC_SPECIAL2,
> +    OPC_MXU_S32SDIV  = 0x17 | OPC_SPECIAL2,
> +    OPC_MXU_D32ADD   = 0x18 | OPC_SPECIAL2,
> +    OPC_MXU_D32ACC   = 0x19 | OPC_SPECIAL2,
> +    OPC_MXU_Q16ACC   = 0x1B | OPC_SPECIAL2,
> +    OPC_MXU_Q8ADDE   = 0x1C | OPC_SPECIAL2,
> +    OPC_MXU_Q8ACCE   = 0x1D | OPC_SPECIAL2,
> +    OPC_MXU_S8LDD    = 0x22 | OPC_SPECIAL2,
> +    OPC_MXU_S8STD    = 0x23 | OPC_SPECIAL2,
> +    OPC_MXU_S8LDI    = 0x24 | OPC_SPECIAL2,
> +    OPC_MXU_S8SDI    = 0x25 | OPC_SPECIAL2,
> +    OPC_MXU_S32EXTR  = 0x26 | OPC_SPECIAL2,
> +    OPC_MXU_D32SARW  = 0x27 | OPC_SPECIAL2,
> +    OPC_MXU_LXB      = 0x28 | OPC_SPECIAL2,
> +    OPC_MXU_S16LDD   = 0x2A | OPC_SPECIAL2,
> +    OPC_MXU_S16STD   = 0x2B | OPC_SPECIAL2,
> +    OPC_MXU_S16LDI   = 0x2C | OPC_SPECIAL2,
> +    OPC_MXU_S16SDI   = 0x2D | OPC_SPECIAL2,
> +    OPC_MXU_S32M2I   = 0x2E | OPC_SPECIAL2,
> +    OPC_MXU_S32I2M   = 0x2F | OPC_SPECIAL2,
> +    OPC_MXU_D32SLL   = 0x30 | OPC_SPECIAL2,
> +    OPC_MXU_D32SLR   = 0x31 | OPC_SPECIAL2,
> +    OPC_MXU_D32SARL  = 0x32 | OPC_SPECIAL2,
> +    OPC_MXU_D32SAR   = 0x33 | OPC_SPECIAL2,
> +    OPC_MXU_Q16SLL   = 0x34 | OPC_SPECIAL2,
> +    OPC_MXU_Q16SLR   = 0x35 | OPC_SPECIAL2,
> +    OPC_MXU_D32SLLV  = 0x36 | OPC_SPECIAL2,
> +    OPC_MXU_Q16SAR   = 0x37 | OPC_SPECIAL2,
> +    OPC_MXU_Q8MUL    = 0x38 | OPC_SPECIAL2,
> +    OPC_MXU_Q8MOVZ   = 0x39 | OPC_SPECIAL2,
> +    OPC_MXU_Q8MAC    = 0x3A | OPC_SPECIAL2,
> +    OPC_MXU_Q16SCOP  = 0x3B | OPC_SPECIAL2,
> +    OPC_MXU_Q8MADL   = 0x3C | OPC_SPECIAL2,
> +    OPC_MXU_S32SFL   = 0x3D | OPC_SPECIAL2,
> +    OPC_MXU_Q8SAD    = 0x3E | OPC_SPECIAL2,
> +};
> +
>  /* Special3 opcodes */
>  #define MASK_SPECIAL3(op)  MASK_OP_MAJOR(op) | (op & 0x3F)