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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2e89e14sm34262915e9.33.2025.01.08.14.05.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Jan 2025 14:05:59 -0800 (PST) Message-ID: <3d54b9c4-cf0f-4e18-955e-a1ebf0fbfdc8@linaro.org> Date: Wed, 8 Jan 2025 23:05:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 28/81] tcg: Add TCGType argument to tcg_out_op To: Richard Henderson , qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org References: <20250107080112.1175095-1-richard.henderson@linaro.org> <20250107080112.1175095-29-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250107080112.1175095-29-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/1/25 09:00, Richard Henderson wrote: > Pass TCGOp.type to the output function. > For aarch64 and tci, use this instead of testing TCG_OPF_64BIT. > For s390x, use this instead of testing INDEX_op_deposit_i64. > For i386, use this to initialize rexw. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.c | 4 ++-- > tcg/aarch64/tcg-target.c.inc | 6 +----- > tcg/arm/tcg-target.c.inc | 2 +- > tcg/i386/tcg-target.c.inc | 9 +++++---- > tcg/loongarch64/tcg-target.c.inc | 2 +- > tcg/mips/tcg-target.c.inc | 2 +- > tcg/ppc/tcg-target.c.inc | 2 +- > tcg/riscv/tcg-target.c.inc | 2 +- > tcg/s390x/tcg-target.c.inc | 7 +++---- > tcg/sparc64/tcg-target.c.inc | 2 +- > tcg/tci/tcg-target.c.inc | 4 ++-- > 11 files changed, 19 insertions(+), 23 deletions(-) > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 64826c7419..e51269f81d 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -2612,12 +2612,12 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > /* no need to flush icache explicitly */ > } > > -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > - const TCGArg args[TCG_MAX_OP_ARGS], > - const int const_args[TCG_MAX_OP_ARGS]) > +static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > + const TCGArg args[TCG_MAX_OP_ARGS], > + const int const_args[TCG_MAX_OP_ARGS]) > { > TCGArg a0, a1, a2; > - int c, const_a2, vexop, rexw = 0; > + int c, const_a2, vexop, rexw; > > #if TCG_TARGET_REG_BITS == 64 > # define OP_32_64(x) \ > @@ -2634,6 +2634,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > a1 = args[1]; > a2 = args[2]; > const_a2 = const_args[2]; > + rexw = type == TCG_TYPE_I32 ? 0 : P_REXW; > > switch (opc) { > case INDEX_op_goto_ptr: Please squash: -- >8 -- diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e51269f81d4..8d1057cdb39 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2622,7 +2622,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, #if TCG_TARGET_REG_BITS == 64 # define OP_32_64(x) \ case glue(glue(INDEX_op_, x), _i64): \ - rexw = P_REXW; /* FALLTHRU */ \ case glue(glue(INDEX_op_, x), _i32) #else # define OP_32_64(x) \ --- With that: Reviewed-by: Philippe Mathieu-Daudé