From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2MBc-0003XX-IS for qemu-devel@nongnu.org; Thu, 03 Nov 2016 13:52:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2MBZ-0002pg-G8 for qemu-devel@nongnu.org; Thu, 03 Nov 2016 13:52:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35514) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c2MBZ-0002pO-9x for qemu-devel@nongnu.org; Thu, 03 Nov 2016 13:52:21 -0400 References: <1478182068-14082-1-git-send-email-laurent@vivier.eu> <06f03abb-3a18-12c3-b359-dcdc0aaeabfe@redhat.com> <32960507-f61e-e3a1-76f3-74a755adb7e3@vivier.eu> From: Paolo Bonzini Message-ID: <3d88d6c0-6730-0db4-c109-a33b9165fb00@redhat.com> Date: Thu, 3 Nov 2016 18:52:15 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , Laurent Vivier , Aurelien Jarno , John Paul Adrian Glaubitz Cc: qemu-devel@nongnu.org On 03/11/2016 17:51, Richard Henderson wrote: >>> Well, tas_test "runs without error with this change", I suppose it fa= ils >>> before? In other words, is this patch enough to run multithreaded sh= 4 >>> programs with qemu-user? >> >> It should,:the problem was reported by Adrian (cc:) while compiling gh= c >> in qemu-sh4, but I have just tested the functionality with the softmmu >> version, not the atomicity. >> >> Adrian, could you test this patch? >=20 > It's a start, but sh4 has an interesting scheme to implement atomic > sequences via special values in the stack pointer. E.g. xchg is >=20 > mova 1f, r0 > mov sp, r1 > mov #(0f-1f), sp > 0: mov.l mem, out > mov.l in, mem > 1: mov r1, sp >=20 > which is only atomic if you've got a UP kernel and have code in your > interrupt entry point that recognizes the small negative value in SP to > reset the PC as necessary. UP kernel =3D no sane way to implement this in user-mode qemu? Doing pattern matching on negative sp moves and the instructions in between is probably not sane, even though GCC always has: - mov/mov for exchange - mov/cmpeq/bf/mov for compare-and-swap - mov/mov/op/mov for fetch-and-foo - mov/mov/and/not/mov for fetch-and-nand - mov/op/mov for foo-and-fetch - mov/and/not/mov for nand-and-fetch Another possibility is to treat the load as a LL and the store as a SC (implemented in turn with cmpxchg+branch if it fails). cmpxchg spans two basic blocks, so maybe one also needs to look at r0 and sp in cpu_get_tb_cpu_state... Anyhow this patch seems like a bugfix. Paolo > For SH4A, there are proper load-locked/store-condition insns, but prior > to that TAS was the only truly atomic insn.