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Thu, 04 Mar 2021 11:13:43 -0800 (PST) Received: from [192.168.1.11] ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id w202sm158918pff.198.2021.03.04.11.13.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Mar 2021 11:13:43 -0800 (PST) Subject: Re: [PATCH 13/44] hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210219144617.4782-1-peter.maydell@linaro.org> <20210219144617.4782-14-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <3da7531f-41fd-d79d-9326-ac9f16a343ee@linaro.org> Date: Thu, 4 Mar 2021 11:13:41 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210219144617.4782-14-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/19/21 6:45 AM, Peter Maydell wrote: > The SSE-300's iokit-sysctl device is similar to the SSE-200, but > some registers have moved address or have different behaviours. > In this commit we add case statements for the registers where > the SSE-300 and SSE-200 have the same behaviour. Some registers > are the same on all SSE versions and so need no code change at all. > Putting both of these categories together covers: > > 0x0 SECDBGSTAT > 0x4 SECDBGSET > 0x8 SECDBGCLR > 0xc SCSECCTRL > 0x10 CLK_CFG0 -- this is like SSE-200 FCLK_DIV but with a > different set of clocks being controlled; our implementation > is a dummy reads-as-written anyway > 0x14 CLK_CFG1 -- similar to SSE-200 SYSCLK_DIV; our implementation > is a dummy > 0x18 CLK_FORCE -- similar to SSE-200 but different bit allocations; > we have a dummy implementation > 0x100 RESET_SYNDROME -- bit allocation differs from SSE-200 but our > implementation is a dummy > 0x104 RESET_MASK -- bit allocation differs from SSE-200 but our > implementation is a dummy > 0x108 SWRESET > 0x10c GRETREG > 0x200 PDCM_PD_SYS_SENSE -- some bit allocations differ, but our > implementation is a dummy > > We also need to migrate the state of these registers which are shared > between the SSE-200 and SSE-300, so update the vmstate 'needed' > function to do this. > > Signed-off-by: Peter Maydell > --- Reviewed-by: Richard Henderson r~