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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id n3-20020a5d6603000000b00333404e9935sm1427192wru.54.2024.01.11.07.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 07:17:26 -0800 (PST) Message-ID: <3dbd3fa1cbad80948175f98dcc0c76b886e2376e.camel@rivosinc.com> Subject: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension From: Rob Bradford To: Andrew Jones Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, ved@rivosinc.com Date: Thu, 11 Jan 2024 15:17:25 +0000 In-Reply-To: <20240111-df7a6acf3109b630469591a1@orel> References: <20240109171848.32237-1-rbradford@rivosinc.com> <20240109171848.32237-2-rbradford@rivosinc.com> <20240111-585fe1291fcaa1e0432674e3@orel> <20240111-df7a6acf3109b630469591a1@orel> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.module_f38+17164+63eeee4a) MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org + Ved On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote: > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > > On Tue, Jan 09, 2024 at 05:07:35PM +0000, Rob Bradford wrote: > > > Add the infrastructure for the 'B' extension which is the union > > > of the > > > Zba, Zbb and Zbs instructions. > > >=20 > > > Signed-off-by: Rob Bradford > > > --- > > > =C2=A0target/riscv/cpu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 5 +++-- > > > =C2=A0target/riscv/cpu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 1 + > > > =C2=A0target/riscv/tcg/tcg-cpu.c | 1 + > > > =C2=A03 files changed, 5 insertions(+), 2 deletions(-) > > >=20 > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index b07a76ef6b..22f8e527ff 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -38,9 +38,9 @@ > > > =C2=A0#include "tcg/tcg.h" > > > =C2=A0 > > > =C2=A0/* RISC-V CPU definitions */ > > > -static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; > > > +static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH"; > >=20 > > Is there a corresponding proposed change to table 29.1 of the > > nonpriv spec > > which states B comes after C and before P? If so, can you provide a > > link > > to it? Otherwise, how do we know that? >=20 > Oh, I see. The unpriv spec B chapter comes after the C chapter (and > before > J, P, ...). I still wonder if we'll have a 29.1 table update with the > ratification of this extension though. >=20 >=20 I agree it's a bit confusing - but the order is established by the table in the unprivileged spec and the table explanation also makes this clear. """ Table 27.1: Standard ISA extension names. The table also defines the canonical order in which extension names must appear in the name string, with top-to-bottom in table indicating first-to-last in the name string, e.g., RV32IMACV is legal, whereas RV32IMAVC is not. """ The proposed B specification does not make any remarks about the ordering in the ISA definition string. [1] I would worry there would be a lot of software churn if this ordering were to be changed. Cheers, Rob > Thanks, > drew [1] - https://github.com/riscv/riscv-b