From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alexey Baturo <baturo.alexey@gmail.com>
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write
Date: Wed, 10 Nov 2021 12:31:50 +0100 [thread overview]
Message-ID: <3dcee028-4020-b8ca-e98c-92af22a5ed9a@linaro.org> (raw)
In-Reply-To: <20211110070452.48539-10-zhiwei_liu@c-sky.com>
On 11/10/21 8:04 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9f41954894..74c0b788fd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
> int csr_priv = get_field(csrno, 0x300);
> int pm_current;
>
> + if (env->debugger) {
> + return false;
> + }
> /*
> * If priv lvls differ that means we're accessing csr from higher priv lvl,
> * so allow the access
Seems reasonable.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-11-10 11:33 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10 9:42 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52 ` Richard Henderson
2021-11-10 13:44 ` LIU Zhiwei
2021-11-10 14:40 ` Richard Henderson
2021-11-11 5:04 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31 ` Richard Henderson [this message]
2021-11-10 7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11 ` Richard Henderson
2021-11-10 14:08 ` LIU Zhiwei
2021-11-10 14:43 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23 ` Richard Henderson
2021-11-10 14:26 ` LIU Zhiwei
2021-11-10 15:01 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27 ` Richard Henderson
2021-11-10 14:38 ` LIU Zhiwei
2021-11-10 15:02 ` Richard Henderson
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