Re: support on risc-v 128bits

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 26/2/24 00:57, Alistair Francis wrote:
> On Mon, Feb 26, 2024 at 9:30 AM Jean-Christophe Énée
> <jean-christophe@blues-softwares.net> wrote:
>>
>> hi,
>> i would like developpe my OS on risc-v 128 bits.
>> after search the support isn´t fully operational
> 
> We have some basic 128-bit support, but it isn't complete. The RISC-V
> spec states:
> 
> ```
> The design of the RV128I base ISA is not yet complete, and while much
> of the remainder of this specification is expected to apply to RV128,
> this version of the document focuses only on RV32 and RV64
> ```
> 
> so the spec isn't finished either. AFAIK there is also no guest
> software we can use for testing.
> 
>>
>> how can i help, and in the same learn risc-v 128 bits
> 
> At this point there isn't really too much to do. There is some basic
> support, so maybe you could try and port your OS to that? I'm not sure
> how you would compile it for 128-bit support though, as I don't think
> any compilers support 128-bits.

You can also have a look at TinyEMU from Fabrice Bellard:

https://bellard.org/tinyemu/readme.txt

- RISC-V system emulator supporting the RV128IMAFDQC base ISA (user
   level ISA version 2.2, priviledged architecture version 1.10)
   including:

   - 32/64/128 bit integer registers
   - 32/64/128 bit floating point instructions
   - Compressed instructions
   - dynamic XLEN change

...

4) Technical notes
------------------

4.1) 128 bit support

The RISC-V specification does not define all the instruction encodings
for the 128 bit integer and floating point operations. The missing
ones were interpolated from the 32 and 64 ones.

Unfortunately there is no RISC-V 128 bit toolchain nor OS now
(volunteers for the Linux port ?), so rv128test.bin may be the first
128 bit code for RISC-V !