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([2001:8003:c020:6900:12c1:9684:874a:fb3a]) by smtp.gmail.com with ESMTPSA id m10-20020a170902db0a00b001d0b4693539sm12436231plx.189.2023.12.27.13.08.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Dec 2023 13:08:44 -0800 (PST) Message-ID: <3de06a76-a409-4810-8113-715bfa1a645e@linaro.org> Date: Thu, 28 Dec 2023 08:08:42 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/35] target/arm: Set CTR_EL0.{IDC, DIC} for the 'max' CPU Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20231218113305.2511480-1-peter.maydell@linaro.org> <20231218113305.2511480-3-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20231218113305.2511480-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/18/23 22:32, Peter Maydell wrote: > The CTR_EL0 register has some bits which allow the implementation to > tell the guest that it does not need to do cache maintenance for > data-to-instruction coherence and instruction-to-data coherence. > QEMU doesn't emulate caches and so our cache maintenance insns are > all NOPs. > > We already have some models of specific CPUs where we set these bits > (e.g. the Neoverse V1), but the 'max' CPU still uses the settings it > inherits from Cortex-A57. Set the bits for 'max' as well, so the > guest doesn't need to do unnecessary work. > > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson r~