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From: "mar.krzeminski" <mar.krzeminski@gmail.com>
To: Francisco Iglesias <frasse.iglesias@gmail.com>, qemu-devel@nongnu.org
Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se
Subject: Re: [Qemu-devel] [PATCH v3 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60)
Date: Wed, 25 Oct 2017 16:55:37 +0200	[thread overview]
Message-ID: <3e0fa080-b53f-3af5-9940-858bbed188ba@gmail.com> (raw)
In-Reply-To: <20171024195139.28179-4-frasse.iglesias@gmail.com>



W dniu 24.10.2017 o 21:51, Francisco Iglesias pisze:
> Add support for the bank address register access commands (BRRD/BRWR) and
> the BULK_ERASE (0x60) command.
>
> Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> ---
>   hw/block/m25p80.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index c85e8fa..3d2975c 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -331,6 +331,8 @@ typedef enum {
>       WRDI = 0x4,
>       RDSR = 0x5,
>       WREN = 0x6,
> +    BRRD = 0x16,
> +    BRWR = 0x17,
Above commands look to be equivalent to 
EXTEND_ADDR_READ/EXTEND_ADDR_WRITE from Micron.
IMO both could fall in the same case block.

>       JEDEC_READ = 0x9f,
>       BULK_ERASE = 0xc7,
>       READ_FSR = 0x70,
> @@ -368,6 +370,8 @@ typedef enum {
>       EN_4BYTE_ADDR = 0xB7,
>       EX_4BYTE_ADDR = 0xE9,
>   
> +    BULK_ERASE_60 = 0x60,
> +
>       EXTEND_ADDR_READ = 0xC8,
>       EXTEND_ADDR_WRITE = 0xC5,
>   
> @@ -975,6 +979,15 @@ static void decode_new_cmd(Flash *s, uint32_t value)
>           }
>           break;
>   
> +    case BRWR:
> +        if (s->write_enable) {
> +            s->needed_bytes = 1;
> +            s->pos = 0;
> +            s->len = 0;
> +            s->state = STATE_COLLECTING_DATA;
> +        }
> +        break;
> +
>       case WRDI:
>           s->write_enable = false;
>           break;
> @@ -1004,6 +1017,12 @@ static void decode_new_cmd(Flash *s, uint32_t value)
>           s->state = STATE_READING_DATA;
>           break;
>   
> +    case BRRD:
> +        s->pos = 0;
> +        s->len = 1;
> +        s->state = STATE_READING_DATA;
> +        break;
> +
I can not see any code where you are actually filling the register 
value. s->ear could be used for that as well.
>       case JEDEC_READ:
>           DB_PRINT_L(0, "populated jedec code\n");
>           for (i = 0; i < s->pi->id_len; i++) {
> @@ -1038,6 +1057,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
>           }
>           break;
>   
> +    case BULK_ERASE_60:
>       case BULK_ERASE:
>           if (s->write_enable) {
>               DB_PRINT_L(0, "chip erase\n");
Regards,
Marcin

  reply	other threads:[~2017-10-25 14:55 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-24 19:51 [Qemu-devel] [PATCH v3 00/13] Add support for the ZynqMP Generic QSPI Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR Francisco Iglesias
2017-10-25 18:03   ` mar.krzeminski
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands Francisco Iglesias
2017-10-25 18:12   ` mar.krzeminski
2017-10-25 21:03     ` francisco iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) Francisco Iglesias
2017-10-25 14:55   ` mar.krzeminski [this message]
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 04/13] m25p80: Add support for n25q512a11 and n25q512a13 Francisco Iglesias
2017-10-25 18:02   ` mar.krzeminski
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 06/13] xilinx_spips: Update striping to be big-endian bit order Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI Francisco Iglesias
2017-10-24 19:51 ` [Qemu-devel] [PATCH v3 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI Francisco Iglesias
2017-10-24 20:04 ` [Qemu-devel] [PATCH v3 09/13] xilinx_spips: Add support for zero pumping Francisco Iglesias
2017-11-02 23:59 ` [Qemu-devel] [PATCH v7 " Francisco Iglesias

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