[Qemu-devel] PATCH: Fix Sparc32 save & load

["Luis Pureza" <pureza@student.dei.uc.pt>]

[-- Attachment #1: Type: text/plain, Size: 573 bytes --]

The following patch fixes some issues with Sparc32 save & load operations.

The most significant change is the call to cpu_set_cwp(), just prior
to saving, to make sure the overflow registers are copied to the first
window if the cwp is the last window. Thus, on load, all registers
will have the correct values.

Also, I'm saving & loading two more fields of the CPUState -
interrupt_index and pil_in. I wonder if these are enough.

Finally, on SPARC64 saving code, I noticed a call to qemu_get_ptimer()
and replaced it with qemu_put_ptimer().

Best regards,

Luis Pureza

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: Fix_Sparc32_load_restore.patch --]
[-- Type: text/x-diff; name=Fix_Sparc32_load_restore.patch, Size: 1276 bytes --]

Index: target-sparc/machine.c
===================================================================
--- target-sparc/machine.c	(revision 4975)
+++ target-sparc/machine.c	(working copy)
@@ -31,6 +31,10 @@
     int i;
     uint32_t tmp;
 
+    // if env->cwp == env->nwindows - 1, this will set the ins of the last
+    // window as the outs of the first window
+    cpu_set_cwp(env, env->cwp);
+
     for(i = 0; i < 8; i++)
         qemu_put_betls(f, &env->gregs[i]);
     qemu_put_be32s(f, &env->nwindows);
@@ -54,6 +58,8 @@
     qemu_put_be32(f, tmp);
     qemu_put_betls(f, &env->fsr);
     qemu_put_betls(f, &env->tbr);
+    qemu_put_be32s(f, &env->interrupt_index);
+    qemu_put_be32s(f, &env->pil_in);
 #ifndef TARGET_SPARC64
     qemu_put_be32s(f, &env->wim);
     /* MMU */
@@ -110,7 +116,7 @@
     qemu_put_be64s(f, &env->hver);
     qemu_put_be64s(f, &env->hstick_cmpr);
     qemu_put_be64s(f, &env->ssr);
-    qemu_get_ptimer(f, env->hstick);
+    qemu_put_ptimer(f, env->hstick);
 #endif
 }
 
@@ -147,6 +153,8 @@
     PUT_PSR(env, tmp);
     qemu_get_betls(f, &env->fsr);
     qemu_get_betls(f, &env->tbr);
+    qemu_get_be32s(f, &env->interrupt_index);
+    qemu_get_be32s(f, &env->pil_in);
 #ifndef TARGET_SPARC64
     qemu_get_be32s(f, &env->wim);
     /* MMU */