From: Richard Henderson <richard.henderson@linaro.org>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, qemu-devel@nongnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Date: Sun, 5 Sep 2021 10:11:44 +0200 [thread overview]
Message-ID: <3e608998-3270-cf41-66b5-32158db99de0@linaro.org> (raw)
In-Reply-To: <20210904203516.2570119-4-philipp.tomsich@vrull.eu>
On 9/4/21 10:35 PM, Philipp Tomsich wrote:
> Assume clzw being executed on a register that is not sign-extended, such
> as for the following sequence that uses (1ULL << 63) | 392 as the operand
> to clzw:
> bseti a2, zero, 63
> addi a2, a2, 392
> clzw a3, a2
> The correct result of clzw would be 23, but the current implementation
> returns -32 (as it performs a 64bit clz, which results in 0 leading zero
> bits, and then subtracts 32).
>
> Fix this by changing the implementation to:
> 1. shift the original register up by 32
> 2. performs a target-length (64bit) clz
> 3. return 32 if no bits are set
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v10:
> - New patch, fixing correctnes for clzw called on a register with undefined
> (as in: not properly sign-extended) upper bits.
But we have
return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
should *not* be undefined. Ah, what's missing is
ctx->w = true;
within trans_clzw to cause the extend to take effect.
There are a few other "w" functions that are missing that set, though they use EXT_NONE so
there is no visible bug, it would probably be best to set w anyway.
r~
next prev parent reply other threads:[~2021-09-05 8:14 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-04 20:34 [PATCH v10 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-05 8:03 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:13 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-05 8:06 ` Richard Henderson
2021-09-06 5:45 ` Alistair Francis
2021-09-08 5:14 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-05 8:11 ` Richard Henderson [this message]
2021-09-05 9:01 ` Philipp Tomsich
2021-09-10 13:36 ` Philipp Tomsich
2021-09-10 13:40 ` Richard Henderson
2021-09-10 13:47 ` Philipp Tomsich
2021-09-10 13:57 ` Richard Henderson
2021-09-04 20:35 ` [PATCH v10 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-08 5:16 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-08 5:22 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-08 5:19 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-08 5:21 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-08 5:22 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-08 5:24 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-08 5:25 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-04 20:35 ` [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-08 5:27 ` Bin Meng
2021-09-04 20:35 ` [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
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