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References: <cover.1542321076.git.alistair.francis@wdc.com>
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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <3ea3567c-1ca0-1853-eebb-7914a750b5a4@linaro.org>
Date: Fri, 16 Nov 2018 18:29:13 +0100
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Subject: Re: [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:37 PM, Alistair Francis wrote:
> +    /* Detect store by reading the instruction at the program
> +       counter. Note: we currently only generate 32-bit
> +       instructions so we thus only detect 32-bit stores */

Actually, you need to handle what the compiler generates too.  So, if
__riscv_compressed is defined, you need to handle it.


r~