From: Paolo Bonzini <pbonzini@redhat.com>
To: Paul Brook <paul@nowt.org>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Cc: "open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 07/42] Enforce VEX encoding restrictions
Date: Wed, 27 Apr 2022 11:08:19 +0200 [thread overview]
Message-ID: <3ecf4bfb-1373-90b7-f669-a603c2030c9a@redhat.com> (raw)
In-Reply-To: <20220424220204.2493824-8-paul@nowt.org>
On 4/25/22 00:01, Paul Brook wrote:
> +/* If a VEX prefix is used then it must have V=1111b */
> +#define CHECK_AVX_V0(s) do { \
> + CHECK_AVX(s); \
> + if ((s->prefix & PREFIX_VEX) && (s->vex_v != 0)) \
> + goto illegal_op; \
> + } while (0)
> +
What do you think about
#define CHECK_AVX(s, flags) \
do {
if ((s->prefix & PREFIX_VEX) && !(env->hflags & HF_AVX_EN_MASK)) {
goto illegal_op;
}
if ((flags) & SSE_OPF_AVX2) {
CHECK_AVX2(s);
}
if ((flags) & SSE_OPF_AVX_128) {
CHECK_AVX_128(s);
}
if ((flags) & SSE_OPF_V0) {
CHECK_V0(s);
}
}
Macros such as CHECK_AVX_V0_128(s) would become CHECK_AVX(s, SSE_OPF_V0
| SSE_OPF_AVX_128); a bit longer but still bearable. And here you would
have:
> case 0x210: /* movss xmm, ea */
> if (mod != 3) {
> + CHECK_AVX_V0_128(s);
> gen_lea_modrm(env, s, modrm);
> gen_op_ld_v(s, MO_32, s->T0, s->A0);
> tcg_gen_st32_tl(s->T0, cpu_env,
> @@ -3379,6 +3432,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
> tcg_gen_st32_tl(s->T0, cpu_env,
> offsetof(CPUX86State, xmm_regs[reg].ZMM_L(3)));
> } else {
> + CHECK_AVX_128(s);
CHECK_AVX(s, SSE_OPF_AVX_128);
if (mod != 3) {
CHECK_V0(s);
...
} else {
...
}
Another possibility is to add SSE_OPF_V0_MEM (i.e. V0 if mod != 3), and use
CHECK_AVX(s, SSE_OPF_AVX_128 | SSE_OPF_AVX_V0_MEM);
It's okay not to move _all_ flags checks in the macros, but for example
here:
> + if (op6.ext_mask == CPUID_EXT_AVX
> + && (s->prefix & PREFIX_VEX) == 0) {
> + goto illegal_op;
> + }
> + if (op6.flags & SSE_OPF_AVX2) {
> + CHECK_AVX2(s);
> + }
> +
> if (b1) {
> + if (op6.flags & SSE_OPF_V0) {
> + CHECK_AVX_V0(s);
> + } else {
> + CHECK_AVX(s);
> + }
> op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
> +
> + if (op6.flags & SSE_OPF_MMX) {
> + CHECK_AVX2_256(s);
> + }
there is a lot of room for using a flags-extended CHECK_AVX macro.
Also, SSE_OPF_V0 seems overloaded, because it means depending on the
place in the code:
- always 2-operand
- 2-operand except if SCALAR && !CMP
- 2-operand except if SCALAR && !CMP && has REPZ/REPNZ prefixes
It is not clear to me if the former overlaps with the last (i.e. if
there are any SCALAR && !CMP operations that are always 2-operand). If
so, please use different constants for all three; if not, please use a
different constant for the last, e.g. SSE_OPF_V0 and SSE_OPF_VEC_V0, so
that the difference is visible in the flags-extended CHECK_AVX macro.
Also related to overloading, here and in patch 37 there is code like this:
> + if (op7.flags & SSE_OPF_BLENDV && !(s->prefix & PREFIX_VEX)) {
> + /* Only VEX encodings are valid for these blendv opcodes */
> + goto illegal_op;
> + }
If this is for all SSE_OPF_BLENDV operations, it can be handled in the
flags-enabled CHECK_AVX() macro above. If it is only for some, it
should be a new flag SSE_OPF_VEX_ONLY.
Finally (replying here just to keep things together), patch 29 has "We
abuse the SSE_OPF_SCALAR flag to select the memory operand width
appropriately". Please don't; use a separate function that takes in "b"
and returns a bool, with just a switch statement in it.
> + CHECK_AVX(s);
> + scalar_op = (s->prefix & PREFIX_VEX)
> + && (op7.flags & SSE_OPF_SCALAR)
> + && !(op7.flags & SSE_OPF_CMP);
> + if (is_xmm && (op7.flags & SSE_OPF_MMX)) {
> + CHECK_AVX2_256(s);
> + }
I think the is_xmm check is always true here (inside case 0x03a: case
0x13a:, i.e. b is inside the 0x10..0x5f range)?
Paolo
next prev parent reply other threads:[~2022-04-27 9:14 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-18 17:39 [PATCH 0/3] AVX guest implementation Paul Brook
2022-04-18 17:39 ` [PATCH 1/4] Add AVX_EN hflag Paul Brook
2022-04-18 17:39 ` [PATCH 2/4] TCG support for AVX Paul Brook
2022-04-18 19:33 ` Peter Maydell
2022-04-18 19:45 ` Paul Brook
2022-04-18 19:50 ` Peter Maydell
2022-04-18 23:14 ` Richard Henderson
2022-04-20 14:19 ` Paolo Bonzini
2022-04-20 18:59 ` Paul Brook
2022-04-18 17:39 ` [PATCH 3/4] Enable all x86-64 cpu features in user mode Paul Brook
2022-04-18 17:39 ` [PATCH 4/4] AVX tests Paul Brook
2022-04-19 10:34 ` Alex Bennée
2022-04-24 22:01 ` [PATCH v2 01/42] i386: pcmpestr 64-bit sign extension bug Paul Brook
2022-04-25 15:50 ` Richard Henderson
2022-04-27 7:00 ` Paolo Bonzini
2022-04-24 22:01 ` [PATCH v2 02/42] i386: DPPS rounding fix Paul Brook
2022-04-25 16:09 ` Richard Henderson
2022-04-24 22:01 ` [PATCH v2 03/42] Add AVX_EN hflag Paul Brook
2022-04-25 17:27 ` Richard Henderson
2022-04-24 22:01 ` [PATCH v2 04/42] i386: Rework sse_op_table1 Paul Brook
2022-04-24 22:01 ` [PATCH v2 05/42] i386: Rework sse_op_table6/7 Paul Brook
2022-04-24 22:01 ` [PATCH v2 06/42] i386: Add CHECK_NO_VEX Paul Brook
2022-04-25 20:39 ` Richard Henderson
2022-04-25 20:41 ` Richard Henderson
2022-04-24 22:01 ` [PATCH v2 07/42] Enforce VEX encoding restrictions Paul Brook
2022-04-25 20:42 ` Richard Henderson
2022-04-25 21:00 ` Richard Henderson
2022-04-27 9:08 ` Paolo Bonzini [this message]
2022-04-24 22:01 ` [PATCH v2 08/42] i386: Add ZMM_OFFSET macro Paul Brook
2022-04-25 21:03 ` Richard Henderson
2022-04-24 22:01 ` [PATCH v2 09/42] i386: Helper macro for 256 bit AVX helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 10/42] i386: Rewrite vector shift helper Paul Brook
2022-04-25 21:33 ` Richard Henderson
2022-04-27 6:51 ` Paolo Bonzini
2022-04-24 22:01 ` [PATCH v2 11/42] i386: Rewrite simple integer vector helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 12/42] i386: Misc integer AVX helper prep Paul Brook
2022-04-24 22:01 ` [PATCH v2 13/42] i386: Destructive vector helpers for AVX Paul Brook
2022-04-27 6:53 ` Paolo Bonzini
2022-04-24 22:01 ` [PATCH v2 14/42] i386: Add size suffix to vector FP helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 15/42] i386: Floating point atithmetic helper AVX prep Paul Brook
2022-04-24 22:01 ` [PATCH v2 16/42] i386: Dot product AVX helper prep Paul Brook
2022-04-24 22:01 ` [PATCH v2 17/42] i386: Destructive FP helpers for AVX Paul Brook
2022-04-24 22:01 ` [PATCH v2 18/42] i386: Misc AVX helper prep Paul Brook
2022-04-24 22:01 ` [PATCH v2 19/42] i386: Rewrite blendv helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 20/42] i386: AVX pclmulqdq Paul Brook
2022-04-24 22:01 ` [PATCH v2 21/42] i386: AVX+AES helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 22/42] i386: Update ops_sse_helper.h ready for 256 bit AVX Paul Brook
2022-04-24 22:01 ` [PATCH v2 23/42] i386: AVX comparison helpers Paul Brook
2022-04-24 22:01 ` [PATCH v2 24/42] i386: Move 3DNOW decoder Paul Brook
2022-04-24 22:01 ` [PATCH v2 25/42] i386: VEX.V encodings (3 operand) Paul Brook
2022-04-24 22:01 ` [PATCH v2 26/42] i386: Utility function for 128 bit AVX Paul Brook
2022-04-24 22:01 ` [PATCH v2 27/42] i386: Translate 256 bit AVX instructions Paul Brook
2022-04-24 22:01 ` [PATCH v2 28/42] i386: Implement VZEROALL and VZEROUPPER Paul Brook
2022-04-24 22:01 ` [PATCH v2 29/42] i386: Implement VBROADCAST Paul Brook
2022-04-24 22:01 ` [PATCH v2 30/42] i386: Implement VPERMIL Paul Brook
2022-04-24 22:01 ` [PATCH v2 31/42] i386: Implement AVX variable shifts Paul Brook
2022-04-24 22:01 ` [PATCH v2 32/42] i386: Implement VTEST Paul Brook
2022-04-24 22:01 ` [PATCH v2 33/42] i386: Implement VMASKMOV Paul Brook
2022-04-24 22:01 ` [PATCH v2 34/42] i386: Implement VGATHER Paul Brook
2022-04-24 22:01 ` [PATCH v2 35/42] i386: Implement VPERM Paul Brook
2022-04-24 22:01 ` [PATCH v2 36/42] i386: Implement VINSERT128/VEXTRACT128 Paul Brook
2022-04-24 22:01 ` [PATCH v2 37/42] i386: Implement VBLENDV Paul Brook
2022-04-24 22:02 ` [PATCH v2 38/42] i386: Implement VPBLENDD Paul Brook
2022-04-24 22:02 ` [PATCH v2 39/42] i386: Enable AVX cpuid bits when using TCG Paul Brook
2022-04-24 22:02 ` [PATCH v2 40/42] Enable all x86-64 cpu features in user mode Paul Brook
2022-04-24 22:02 ` [PATCH v2 41/42] AVX tests Paul Brook
2022-04-24 22:02 ` [PATCH v2 42/42] i386: Add sha512-avx test Paul Brook
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3ecf4bfb-1373-90b7-f669-a603c2030c9a@redhat.com \
--to=pbonzini@redhat.com \
--cc=eduardo@habkost.net \
--cc=paul@nowt.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).