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From: "Cédric Le Goater" <clg@kaod.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Daniel P. Berrangé" <berrange@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	qemu-arm@nongnu.org, "Thomas Huth" <thuth@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [RFC PATCH 3/4] hw/arm/aspeed: Replace TARGET_AARCH64 by legacy_binary_is_64bit()
Date: Wed, 5 Mar 2025 17:33:26 +0100	[thread overview]
Message-ID: <3eef4f0d-b931-473d-8e69-4b8c46b6485a@kaod.org> (raw)
In-Reply-To: <20250305161248.54901-4-philmd@linaro.org>

On 3/5/25 17:12, Philippe Mathieu-Daudé wrote:
> For legacy ARM binaries, legacy_binary_is_64bit() is
> equivalent of the compile time TARGET_AARCH64 definition.
> 
> Use it as TypeInfo::registerable() callback to dynamically
> add Aarch64 specific types in qemu-system-aarch64 binary,
> removing the need of TARGET_AARCH64 #ifdef'ry.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/arm/aspeed.c | 8 ++------
>   1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 98bf071139b..3f18a4501e0 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -28,6 +28,7 @@
>   #include "hw/loader.h"
>   #include "qemu/error-report.h"
>   #include "qemu/units.h"
> +#include "qemu/legacy_binary_info.h"
>   #include "hw/qdev-clock.h"
>   #include "system/system.h"
>   
> @@ -179,11 +180,9 @@ struct AspeedMachineState {
>   #define AST2600_EVB_HW_STRAP1 0x000000C0
>   #define AST2600_EVB_HW_STRAP2 0x00000003
>   
> -#ifdef TARGET_AARCH64
>   /* AST2700 evb hardware value */
>   #define AST2700_EVB_HW_STRAP1 0x000000C0
>   #define AST2700_EVB_HW_STRAP2 0x00000003
> -#endif
>   
>   /* Rainier hardware value: (QEMU prototype) */
>   #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
> @@ -1661,7 +1660,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
>       aspeed_machine_class_init_cpus_defaults(mc);
>   }
>   
> -#ifdef TARGET_AARCH64
>   static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
>   {
>       AspeedSoCState *soc = bmc->soc;
> @@ -1690,7 +1688,6 @@ static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
>       mc->default_ram_size = 1 * GiB;
>       aspeed_machine_class_init_cpus_defaults(mc);
>   }
> -#endif
>   
>   static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
>                                                        void *data)
> @@ -1813,12 +1810,11 @@ static const TypeInfo aspeed_machine_types[] = {
>           .name           = MACHINE_TYPE_NAME("ast1030-evb"),
>           .parent         = TYPE_ASPEED_MACHINE,
>           .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
> -#ifdef TARGET_AARCH64
>       }, {
>           .name          = MACHINE_TYPE_NAME("ast2700-evb"),
>           .parent        = TYPE_ASPEED_MACHINE,
> +        .registerable   = legacy_binary_is_64bit,

where is this routine implemented ?

Thanks,

C.


>           .class_init    = aspeed_machine_ast2700_evb_class_init,
> -#endif
>       }, {
>           .name          = TYPE_ASPEED_MACHINE,
>           .parent        = TYPE_MACHINE,



  reply	other threads:[~2025-03-05 16:34 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-05 16:12 [RFC PATCH 0/4] hw/arm: Register target-specific QOM types at runtime Philippe Mathieu-Daudé
2025-03-05 16:12 ` [RFC PATCH 1/4] qom: Introduce TypeInfo::registerable() callback Philippe Mathieu-Daudé
2025-03-05 16:47   ` Pierrick Bouvier
2025-03-06  1:34   ` Richard Henderson
2025-03-05 16:12 ` [RFC PATCH 2/4] hw/arm/raspi: Replace TARGET_AARCH64 by legacy_binary_is_64bit() Philippe Mathieu-Daudé
2025-03-05 16:50   ` Pierrick Bouvier
2025-03-05 17:40   ` Thomas Huth
2025-03-05 18:12     ` Cédric Le Goater
2025-03-05 18:35       ` Thomas Huth
2025-03-05 19:07         ` Philippe Mathieu-Daudé
2025-03-05 20:41           ` BALATON Zoltan
2025-03-06  6:12           ` Thomas Huth
2025-03-06  9:21   ` Daniel P. Berrangé
2025-03-06 10:13     ` Peter Maydell
2025-03-05 16:12 ` [RFC PATCH 3/4] hw/arm/aspeed: " Philippe Mathieu-Daudé
2025-03-05 16:33   ` Cédric Le Goater [this message]
2025-03-05 17:07     ` Philippe Mathieu-Daudé
2025-03-05 17:43   ` Thomas Huth
2025-03-05 16:12 ` [RFC PATCH 4/4] hw/ppc: Remove TARGET_PPC64 use in ppc_create_page_sizes_prop() Philippe Mathieu-Daudé
2025-03-05 16:52   ` Pierrick Bouvier
2025-03-05 16:53 ` [RFC PATCH 0/4] hw/arm: Register target-specific QOM types at runtime Pierrick Bouvier

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