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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a5cfabdsm1587559b3a.13.2024.11.14.10.53.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2024 10:53:29 -0800 (PST) Message-ID: <3f4a2c65-f5c7-4da3-9fd0-8ad4b32a480a@linaro.org> Date: Thu, 14 Nov 2024 10:53:29 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 36/54] target/i386: Convert to TCGCPUOps.tlb_fill_align Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241114160131.48616-1-richard.henderson@linaro.org> <20241114160131.48616-37-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241114160131.48616-37-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/14/24 08:01, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/i386/tcg/helper-tcg.h | 6 +++--- > target/i386/tcg/sysemu/excp_helper.c | 28 ++++++++++++++++------------ > target/i386/tcg/tcg-cpu.c | 2 +- > 3 files changed, 20 insertions(+), 16 deletions(-) > > diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h > index 696d6ef016..b2164f41e6 100644 > --- a/target/i386/tcg/helper-tcg.h > +++ b/target/i386/tcg/helper-tcg.h > @@ -79,9 +79,9 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, > void x86_cpu_record_sigbus(CPUState *cs, vaddr addr, > MMUAccessType access_type, uintptr_t ra); > #else > -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > - MMUAccessType access_type, int mmu_idx, > - bool probe, uintptr_t retaddr); > +bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, > + MMUAccessType access_type, int mmu_idx, > + MemOp memop, int size, bool probe, uintptr_t ra); > G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c > index 168ff8e5f3..d23d28fef5 100644 > --- a/target/i386/tcg/sysemu/excp_helper.c > +++ b/target/i386/tcg/sysemu/excp_helper.c > @@ -601,25 +601,29 @@ static bool get_physical_address(CPUX86State *env, vaddr addr, > return true; > } > > -bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, > - MMUAccessType access_type, int mmu_idx, > - bool probe, uintptr_t retaddr) > +bool x86_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *full, vaddr addr, > + MMUAccessType access_type, int mmu_idx, > + MemOp memop, int size, bool probe, > + uintptr_t retaddr) > { > CPUX86State *env = cpu_env(cs); > TranslateResult out; > TranslateFault err; > > + if (addr & ((1 << memop_alignment_bits(memop)) - 1)) { > + if (probe) { > + return false; > + } > + x86_cpu_do_unaligned_access(cs, addr, access_type, mmu_idx, retaddr); > + } > + > if (get_physical_address(env, addr, access_type, mmu_idx, &out, &err, > retaddr)) { > - /* > - * Even if 4MB pages, we map only one 4KB page in the cache to > - * avoid filling it too fast. > - */ > - assert(out.prot & (1 << access_type)); > - tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK, > - out.paddr & TARGET_PAGE_MASK, > - cpu_get_mem_attrs(env), > - out.prot, mmu_idx, out.page_size); > + memset(full, 0, sizeof(*full)); > + full->phys_addr = out.paddr; > + full->prot = out.prot; > + full->lg_page_size = ctz32(out.page_size); > + full->attrs = cpu_get_mem_attrs(env); > return true; > } > > diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c > index cca19cd40e..6fce6227c7 100644 > --- a/target/i386/tcg/tcg-cpu.c > +++ b/target/i386/tcg/tcg-cpu.c > @@ -117,7 +117,7 @@ static const TCGCPUOps x86_tcg_ops = { > .record_sigsegv = x86_cpu_record_sigsegv, > .record_sigbus = x86_cpu_record_sigbus, > #else > - .tlb_fill = x86_cpu_tlb_fill, > + .tlb_fill_align = x86_cpu_tlb_fill_align, > .do_interrupt = x86_cpu_do_interrupt, > .cpu_exec_halt = x86_cpu_exec_halt, > .cpu_exec_interrupt = x86_cpu_exec_interrupt, Reviewed-by: Pierrick Bouvier