From: Auger Eric <eric.auger@redhat.com>
To: Robin Murphy <robin.murphy@arm.com>,
eric.auger.pro@gmail.com, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com
Cc: jean-philippe@linaro.org, mst@redhat.com,
zhangfei.gao@foxmail.com, shameerali.kolothum.thodi@huawei.com,
will@kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Date: Mon, 6 Jul 2020 18:48:19 +0200 [thread overview]
Message-ID: <3f4dce7c-14e9-f97f-1de5-d39a501bd229@redhat.com> (raw)
In-Reply-To: <10bafac8-a230-c545-662c-bcbd9f3902dc@arm.com>
Hi Robin,
On 7/6/20 6:18 PM, Robin Murphy wrote:
> On 2020-07-02 16:26, Eric Auger wrote:
>> Expose the RIL bit so that the guest driver uses range
>> invalidation.
>
> Hmm, this is a v3.2 feature... so strictly, in order to advertise it you
> would need to claim at least v3.1 in SMMU_AIDR and implement all the
> mandatory v3.1 behaviour ;)
AIDR is not modeled at the moment in this emulation code.
I do not see it used in the linux smmuv3 driver either. I can initialize
it to 0x2 for the sake of completeness.
With respect to the 'mandatory features', could you please help me
determining what are they. Most of the features that would impact this
emulation code look optional to me (52bit support, PBHA, MPAM).
This emulation code is tested against the latest linux kernel.
Thanks
Eric
> Robin.
>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> hw/arm/smmuv3-internal.h | 1 +
>> hw/arm/smmuv3.c | 2 ++
>> 2 files changed, 3 insertions(+)
>>
>> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
>> index 5babf72f7d..4e7ec252ed 100644
>> --- a/hw/arm/smmuv3-internal.h
>> +++ b/hw/arm/smmuv3-internal.h
>> @@ -54,6 +54,7 @@ REG32(IDR1, 0x4)
>> REG32(IDR2, 0x8)
>> REG32(IDR3, 0xc)
>> + FIELD(IDR3, RIL, 10, 1);
>> REG32(IDR4, 0x10)
>> REG32(IDR5, 0x14)
>> FIELD(IDR5, OAS, 0, 3);
>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
>> index 89ab11fc36..add4ba4543 100644
>> --- a/hw/arm/smmuv3.c
>> +++ b/hw/arm/smmuv3.c
>> @@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s)
>> s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
>> s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
>> + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
>> +
>> /* 4K and 64K granule support */
>> s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
>> s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
>>
>
prev parent reply other threads:[~2020-07-06 17:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 15:26 [PATCH v2 0/9] SMMUv3.2 Range-based TLB Invalidation Support Eric Auger
2020-07-02 15:26 ` [PATCH v2 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Eric Auger
2020-07-06 13:11 ` Peter Maydell
2020-07-02 15:26 ` [PATCH v2 2/9] hw/arm/smmu-common: Add IOTLB helpers Eric Auger
2020-07-02 15:26 ` [PATCH v2 3/9] hw/arm/smmu: Introduce smmu_get_iotlb_key() Eric Auger
2020-07-06 13:13 ` Peter Maydell
2020-07-02 15:26 ` [PATCH v2 4/9] hw/arm/smmu: Simplify the IOTLB key format Eric Auger
2020-07-06 13:26 ` Peter Maydell
2020-07-06 14:00 ` Auger Eric
2020-07-02 15:26 ` [PATCH v2 5/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Eric Auger
2020-07-02 15:26 ` [PATCH v2 6/9] hw/arm/smmu-common: Manage IOTLB block entries Eric Auger
2020-07-07 15:04 ` Peter Maydell
2020-07-02 15:26 ` [PATCH v2 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Eric Auger
2020-07-02 15:26 ` [PATCH v2 8/9] hw/arm/smmuv3: Get prepared for range invalidation Eric Auger
2020-07-02 15:26 ` [PATCH v2 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 " Eric Auger
2020-07-06 16:18 ` Robin Murphy
2020-07-06 16:48 ` Auger Eric [this message]
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