Re: [PATCH qemu v2 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs

[Richard Henderson <richard.henderson@linaro.org>]

On 6/8/23 19:49, ~jhogberg wrote:
> From: John Högberg<john.hogberg@ericsson.com>
> 
> Unlike architectures with precise self-modifying code semantics
> (e.g. x86) ARM processors do not maintain coherency for instruction
> execution and memory, and require the explicit use of cache
> management instructions as well as an instruction barrier to make
> code updates visible (the latter on every core that is going to
> execute said code).
> 
> While this is required to make JITs work on actual hardware, QEMU
> has gotten away with not handling this since it does not emulate
> caches, and unconditionally invalidates code whenever the softmmu
> or the user-mode page protection logic detects that code has been
> modified.
> 
> Unfortunately the latter does not work in the face of dual-mapped
> code (a common W^X workaround), where one page is executable and
> the other is writable: user-mode has no way to connect one with the
> other as that is only known to the kernel and the emulated
> application.
> 
> This commit works around the issue by invalidating code in
> IC IVAU instructions.
> 
> Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1034
> 
> Co-authored-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: John Högberg<john.hogberg@ericsson.com>
> ---
>   target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 44 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~