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[90.182.62.66]) by smtp.gmail.com with ESMTPSA id d6-20020adffd86000000b0030ae87bd3e3sm16847086wrr.18.2023.06.13.20.52.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jun 2023 20:52:17 -0700 (PDT) Message-ID: <3f4e8ef6-1ee3-4cca-c34d-fb5cf4ff9b2a@linaro.org> Date: Wed, 14 Jun 2023 05:52:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH qemu v2 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs Content-Language: en-US To: ~jhogberg , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org References: <168656283612.26761.9869630057811681568-1@git.sr.ht> From: Richard Henderson In-Reply-To: <168656283612.26761.9869630057811681568-1@git.sr.ht> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.098, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/8/23 19:49, ~jhogberg wrote: > From: John Högberg > > Unlike architectures with precise self-modifying code semantics > (e.g. x86) ARM processors do not maintain coherency for instruction > execution and memory, and require the explicit use of cache > management instructions as well as an instruction barrier to make > code updates visible (the latter on every core that is going to > execute said code). > > While this is required to make JITs work on actual hardware, QEMU > has gotten away with not handling this since it does not emulate > caches, and unconditionally invalidates code whenever the softmmu > or the user-mode page protection logic detects that code has been > modified. > > Unfortunately the latter does not work in the face of dual-mapped > code (a common W^X workaround), where one page is executable and > the other is writable: user-mode has no way to connect one with the > other as that is only known to the kernel and the emulated > application. > > This commit works around the issue by invalidating code in > IC IVAU instructions. > > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1034 > > Co-authored-by: Richard Henderson > Signed-off-by: John Högberg > --- > target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 44 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~