From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: mrolnik@gmail.com, philmd@linaro.org
Subject: Re: [PATCH 09/17] target/avr: Introduce gen_data_{load,store}_raw
Date: Mon, 24 Mar 2025 18:12:53 -0700 [thread overview]
Message-ID: <3f6af01d-97a5-4c6d-b642-a5897aa8ad55@linaro.org> (raw)
In-Reply-To: <20250323173730.3213964-10-richard.henderson@linaro.org>
On 3/23/25 10:37, Richard Henderson wrote:
> Prepare for offset_io being non-zero; also allow folding
> stack pointer offsets into the arithmetic.
> So far, all offsets are 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/avr/translate.c | 42 ++++++++++++++++++++++++++++++++----------
> 1 file changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/target/avr/translate.c b/target/avr/translate.c
> index e9fef1aaad..6bb4154dff 100644
> --- a/target/avr/translate.c
> +++ b/target/avr/translate.c
> @@ -198,6 +198,28 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn);
> static void gen_inb(DisasContext *ctx, TCGv data, int port);
> static void gen_outb(DisasContext *ctx, TCGv data, int port);
>
> +static void gen_data_store_raw(DisasContext *ctx, TCGv data,
> + TCGv addr, int offset, MemOp mop)
> +{
> + if (ctx->offset_io + offset) {
> + TCGv t = tcg_temp_new();
> + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset);
> + addr = t;
> + }
> + tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, mop);
> +}
> +
> +static void gen_data_load_raw(DisasContext *ctx, TCGv data,
> + TCGv addr, int offset, MemOp mop)
> +{
> + if (ctx->offset_io + offset) {
> + TCGv t = tcg_temp_new();
> + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset);
> + addr = t;
> + }
> + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, mop);
> +}
> +
> /*
> * Arithmetic Instructions
> */
> @@ -940,21 +962,21 @@ static void gen_push_ret(DisasContext *ctx, int ret)
> if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> TCGv t0 = tcg_constant_i32(ret & 0x0000ff);
>
> - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
> + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_UB);
> tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> TCGv t0 = tcg_constant_i32(ret & 0x00ffff);
>
> tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW);
> tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> TCGv lo = tcg_constant_i32(ret & 0x0000ff);
> TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);
>
> - tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> + gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB);
> tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
> - tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> + gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW);
> tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
> }
> }
> @@ -963,20 +985,20 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret)
> {
> if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
> tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
> + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB);
> } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
> tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW);
> tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
> TCGv lo = tcg_temp_new_i32();
> TCGv hi = tcg_temp_new_i32();
>
> tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
> - tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
> + gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW);
>
> tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
> - tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
> + gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB);
>
> tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
> }
> @@ -1498,13 +1520,13 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
> if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
> gen_helper_fullwr(tcg_env, data, addr);
> } else {
> - tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
> + gen_data_store_raw(ctx, data, addr, 0, MO_UB);
> }
> }
>
> static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
> {
> - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
> + gen_data_load_raw(ctx, data, addr, 0, MO_UB);
> }
>
> static void gen_inb(DisasContext *ctx, TCGv data, int port)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-03-25 1:39 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-23 17:37 [PATCH 00/17] target/avr: Increase page size Richard Henderson
2025-03-23 17:37 ` [PATCH 01/17] hw/core/cpu: Use size_t for memory_rw_debug len argument Richard Henderson
2025-03-23 21:25 ` Philippe Mathieu-Daudé
2025-03-25 0:43 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 02/17] target/avr: Fix buffer read in avr_print_insn Richard Henderson
2025-03-25 0:52 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 03/17] target/avr: Improve decode of LDS, STS Richard Henderson
2025-03-25 0:53 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 04/17] target/avr: Remove OFFSET_CPU_REGISTERS Richard Henderson
2025-03-23 21:27 ` Philippe Mathieu-Daudé
2025-03-25 0:55 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 05/17] target/avr: Move cpu register accesses into system memory Richard Henderson
2025-03-25 1:07 ` Pierrick Bouvier
2025-03-25 13:48 ` Richard Henderson
2025-03-25 14:34 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 06/17] target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr Richard Henderson
2025-03-25 1:08 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 07/17] target/avr: Use do_stb in avr_cpu_do_interrupt Richard Henderson
2025-03-23 21:31 ` Philippe Mathieu-Daudé
2025-03-25 1:09 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 08/17] target/avr: Add offset-io cpu property Richard Henderson
2025-03-25 1:10 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 09/17] target/avr: Introduce gen_data_{load,store}_raw Richard Henderson
2025-03-25 1:12 ` Pierrick Bouvier [this message]
2025-03-23 17:37 ` [PATCH 10/17] target/avr: Update cpu_sp after push and pop Richard Henderson
2025-03-25 1:36 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 11/17] target/avr: Implement CPUState.memory_rw_debug Richard Henderson
2025-03-23 21:33 ` Philippe Mathieu-Daudé
2025-03-25 1:19 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 12/17] target/avr: Handle offset_io in helper.c Richard Henderson
2025-03-23 21:34 ` Philippe Mathieu-Daudé
2025-03-25 1:20 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 13/17] target/avr: Handle offset_io in avr_cpu_realizefn Richard Henderson
2025-03-23 21:35 ` Philippe Mathieu-Daudé
2025-03-23 21:38 ` Philippe Mathieu-Daudé
2025-03-25 1:20 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 14/17] hw/avr: Set offset_io and increase page size to 1k Richard Henderson
2025-03-25 1:21 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 15/17] hw/avr: Pass mcu_type to class_base_init via .class_data Richard Henderson
2025-03-23 21:38 ` Philippe Mathieu-Daudé
2025-03-25 1:25 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 16/17] hw/avr: Move AtmegaMcuClass to atmega.h Richard Henderson
2025-03-25 1:22 ` Pierrick Bouvier
2025-03-23 17:37 ` [PATCH 17/17] target/avr: Enable TARGET_PAGE_BITS_VARY Richard Henderson
2025-03-25 1:24 ` Pierrick Bouvier
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