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Mon, 24 Mar 2025 18:37:22 -0700 (PDT) Received: from [192.168.1.67] ([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73906158ef2sm9090422b3a.141.2025.03.24.18.37.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 18:37:22 -0700 (PDT) Message-ID: <3f6af01d-97a5-4c6d-b642-a5897aa8ad55@linaro.org> Date: Mon, 24 Mar 2025 18:12:53 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/17] target/avr: Introduce gen_data_{load,store}_raw Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org References: <20250323173730.3213964-1-richard.henderson@linaro.org> <20250323173730.3213964-10-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250323173730.3213964-10-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/23/25 10:37, Richard Henderson wrote: > Prepare for offset_io being non-zero; also allow folding > stack pointer offsets into the arithmetic. > So far, all offsets are 0. > > Signed-off-by: Richard Henderson > --- > target/avr/translate.c | 42 ++++++++++++++++++++++++++++++++---------- > 1 file changed, 32 insertions(+), 10 deletions(-) > > diff --git a/target/avr/translate.c b/target/avr/translate.c > index e9fef1aaad..6bb4154dff 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -198,6 +198,28 @@ static bool decode_insn(DisasContext *ctx, uint16_t insn); > static void gen_inb(DisasContext *ctx, TCGv data, int port); > static void gen_outb(DisasContext *ctx, TCGv data, int port); > > +static void gen_data_store_raw(DisasContext *ctx, TCGv data, > + TCGv addr, int offset, MemOp mop) > +{ > + if (ctx->offset_io + offset) { > + TCGv t = tcg_temp_new(); > + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); > + addr = t; > + } > + tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, mop); > +} > + > +static void gen_data_load_raw(DisasContext *ctx, TCGv data, > + TCGv addr, int offset, MemOp mop) > +{ > + if (ctx->offset_io + offset) { > + TCGv t = tcg_temp_new(); > + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); > + addr = t; > + } > + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, mop); > +} > + > /* > * Arithmetic Instructions > */ > @@ -940,21 +962,21 @@ static void gen_push_ret(DisasContext *ctx, int ret) > if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { > TCGv t0 = tcg_constant_i32(ret & 0x0000ff); > > - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); > + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_UB); > tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { > TCGv t0 = tcg_constant_i32(ret & 0x00ffff); > > tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); > + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW); > tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { > TCGv lo = tcg_constant_i32(ret & 0x0000ff); > TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8); > > - tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); > + gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB); > tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); > - tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); > + gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW); > tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > } > } > @@ -963,20 +985,20 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret) > { > if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { > tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); > + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB); > } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { > tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); > + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW); > tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { > TCGv lo = tcg_temp_new_i32(); > TCGv hi = tcg_temp_new_i32(); > > tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > - tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); > + gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW); > > tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); > - tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); > + gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB); > > tcg_gen_deposit_tl(ret, lo, hi, 8, 16); > } > @@ -1498,13 +1520,13 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) > if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { > gen_helper_fullwr(tcg_env, data, addr); > } else { > - tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); > + gen_data_store_raw(ctx, data, addr, 0, MO_UB); > } > } > > static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) > { > - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); > + gen_data_load_raw(ctx, data, addr, 0, MO_UB); > } > > static void gen_inb(DisasContext *ctx, TCGv data, int port) Reviewed-by: Pierrick Bouvier